V DSS Rds(on) max I D

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1 SMPS MOSFET Applications l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching l Lead-Free Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current TO-220AB PD IRFBN50APbF HEXFET Power MOSFET V DSS Rds(on) max I D 500V 0.52Ω A G D S Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 0V I T C = C Continuous Drain Current, V 0V 7.0 A I DM Pulsed Drain Current 44 P C = 25 C Power Dissipation 70 W Linear Derating Factor.3 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 6.9 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting torqe, 6-32 or M3 screw 0 lbf in (.N m) Applicable Off Line SMPS Topologies: l Two Transistor Forward l Half & Full Bridge l Power Factor Correction Boost Notes through are on page 8 //03

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 500 V V GS = 0V, I D = 250µA R DS(on) Static Drain-to-Source On-Resistance 0.52 Ω V GS = 0V, I D = 6.6A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 500V, V GS = 0V 250 V DS = 400V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage V GS = 30V na Gate-to-Source Reverse Leakage - V GS = -30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 6. S V DS = 50V, I D = 6.6A Q g Total Gate Charge 52 I D = A Q gs Gate-to-Source Charge 3 nc V DS = 400V Q gd Gate-to-Drain ("Miller") Charge 8 V GS = 0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 4 V DD = 250V t r Rise Time 35 ns I D = A t d(off) Turn-Off Delay Time 32 R G = 9.Ω t f Fall Time 28 R D = 22Ω,See Fig. 0 C iss Input Capacitance 423 V GS = 0V C oss Output Capacitance 208 V DS = 25V C rss Reverse Transfer Capacitance 8. pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 2000 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 55 V GS = 0V, V DS = 400V, ƒ =.0MHz C oss eff. Effective Output Capacitance 97 V GS = 0V, V DS = 0V to 400V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 275 mj I AR Avalanche Current A E AR Repetitive Avalanche Energy 7 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 44 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = A Q rr Reverse RecoveryCharge µc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2

3 I D, Drain-to-Source Current (A) 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I D, Drain-to-Source Current (A) 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH 4.5V T J = 50 C 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 0 T J = 50 C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = A V GS = 0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance (pf) 2400 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd 2000 C oss = C ds Cgd C iss 600 C oss C rss A 0 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) I = D A 6.6A V DS = 400V V DS = 250V V DS = V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 0 T J = 50 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 0 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us us ms 0ms TC = 25 C TJ = 50 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 2 V DS R D I D, Drain Current (A) R G V GS 0V Pulse Width µs Duty Factor 0. % D.U.T. Fig 0a. Switching Time Test Circuit - V DD 2 V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = PDM t 0.02 SINGLE PULSE t2 0.0 (THERMAL RESPONSE) Notes:. Duty factor D = t / t Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 5V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS tp I AS Fig 2b. Unclamped Inductive Waveforms Q G E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 4.9A 7.0A A Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avalanche Energy Vs. Drain Current 0 V Q GS Q GD 660 V G 2V V GS Current Regulator Same Type as D.U.T..2µF 50KΩ 3mA.3µF Charge Fig 3a. Basic Gate Charge Waveform D.U.T. V - DS V DSav, Avalanche Voltage (V) A I av, Avalanche Current (A) I G I D Current Sampling Resistors Fig 2d. Typical Drain-to-Source Voltage Fig 3b. Gate Charge Test Circuit Vs. Avalanche Current 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS 7

8 TO-220AB Package Outline 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) - A (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) (.255) 6.0 (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE 2 - DRAIN - GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR.40 (.055) 3X.5 (.045) 2.54 (.) 2X 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.04) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: T HIS IS AN IRF00 LOT CODE 789 ASS EMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO ASS EMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 997 WEE K 9 LINE C Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 4.5mH R G = 25Ω, I AS = A. (See Figure 2) ƒ I SD A, di/dt 40A/µs, V DD V (BR)DSS, T J 50 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) Visit us at for sales contact information./03 8

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