NTMS4920NR2G. Power MOSFET 30 V, 17 A, N Channel, SO 8 Features

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1 NTMS9N Power MOSFET 3 V, 7 A, N Channel, SO Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant Applications DC DC Converters Points of Loads Power Load Switch Motor Controls MAXIMUM RATINGS ( unless otherwise stated) Parameter Symbol Value Unit to Voltage V DSS 3 V Gate to Voltage V GS ± V Continuous T A = C I D. A Current R JA (Note ) T A = 7 C.3 Power Dissipation R JA (Note ) Continuous Current R JA (Note ) Power Dissipation R JA (Note ) Continuous Current R JA, t s (Note ) Power Dissipation R JA, t s(note ) T A = C P D.6 W T A = C I D.6 A T A = 7 C. T A = C P D. W T A = C I D 7 A T A = 7 C 3.6 T A = C P D. W Pulsed Current T A = C, t p = s I DM 36 A Operating Junction and Storage Temperature T J, T stg to C Current (Body Diode) I S. A Single Pulse to Avalanche Energy (, V DD = 3 V, V GS = V, I L = A pk, L =. mh, R G = ) Lead Temperature for Soldering Purposes (/ from case for s) E AS 6 mj T L 6 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction to Ambient (Note ) R JA. C/W Junction to Ambient t s (Note ) R JA 9 Junction to Foot () R JF Junction to Ambient (Note ) R JA. Surfacemounted on FR board using in sq pad size (Cu area =.7 in sq [ oz] including traces).. Surfacemounted on FR board using the minimum recommended pad size. V (BR)DSS R DS(ON) MAX I D MAX 3 V SO CASE 7 STYLE G.3 V.7 V N Channel D ORDERING INFORMATION 7 A Device Package Shipping NTMS9NRG For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. S MARKING DIAGRAM/ PIN ASSIGNMENT Gate SO (Pb Free) 9N AYWW Top View 9N = Device Code A = Assembly Location Y = Year WW = Work Week = Pb Free Package (Note: Microdot may be in either location) /Tape & Reel Semiconductor Components Industries, LLC, 9 September, 9 Rev. Publication Order Number: NTMS9N/D

2 NTMS9N ELECTRICAL CHARACTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS to Breakdown Voltage V (BR)DSS V GS = V, I D = A 3 V to Breakdown Voltage Temperature Coefficient V (BR)DSS /T J. mv/ C Zero Gate Voltage Current I DSS V GS = V, V DS = V. A T J = C Gate to Leakage Current I GSS V DS = V, V GS = ± V ± na ON CHARACTERISTICS (Note 3) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = A. 3. V Negative Threshold Temperature Coefficient V GS(TH) /T J. mv/ C Forward Diode Voltage V to On Resistance R DS(on) V GS = V, I D = 7. A m V GS =. V, I D = 6. A.6.7 Forward Transconductance g FS V DS =. V, I D = 7. A 3. S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance C iss 6 pf Output Capacitance C oss V GS = V, f =. MHz, V DS = V 7 Reverse Transfer Capacitance C rss Total Gate Charge Q G(TOT) 6.3 nc Threshold Gate Charge Q G(TH) 6. Gate to Charge Q GS V GS =. V, V DS = V, I D = 7. A. Gate to Charge Q GD 3. Total Gate Charge Q G(TOT) V GS = V, V DS = V, I D = 7. A.9 nc SWITCHING CHARACTERISTICS (Note ) Turn On Delay Time t d(on).3 ns Rise Time t r V GS = V, V DS = V,.7 Turn Off Delay Time t d(off) I D =. A, R G = Fall Time t f. DRAIN SOURCE DIODE CHARACTERISTICS.7. V SD V GS = V, I S =. A T J = C.3 Reverse Recovery Time t RR.3 ns Charge Time t a V GS = V, d IS /d t = A/ s,.7 Discharge Time t b I S =. A.6 Reverse Recovery Charge Q RR 6 nc PACKAGE PARASITIC VALUES Inductance L S.66 nh Inductance L D T A = C. Gate Inductance L G. Gate Resistance R G.. 3. Pulse Test: pulse width = 3 s, duty cycle %.. Switching characteristics are independent of operating junction temperatures.

3 I D, DRAIN CURRENT (AMPS) NTMS9N TYPICAL PERFORMANCE CURVES V 6 V DS V 3. V V. V 3. V 3 V.6 V T J = C. V 6 V. V T J = C I D, DRAIN CURRENT (AMPS) V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I D = 7. A. 6 V GS, GATE TO SOURCE VOLTAGE (VOLTS) R DS(on), DRAIN TO SOURCE RESISTANCE ( ) V GS =. V V GS = V I D, DRAIN CURRENT (AMPS) Figure 3. On Resistance vs. Gate to Voltage Figure. On Resistance vs. Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) V GS = V I D = 7. A I DSS, LEAKAGE (na) V GS = V T J = C T J = C.6 7 T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature 3 Figure 6. to Leakage Current vs. Voltage 3

4 C, CAPACITANCE (pf) 3 3 C iss C oss C rss DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation NTMS9N TYPICAL PERFORMANCE CURVES V GS = V V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 Q GS Q GD V GS = V I D = 7. A Q G, TOTAL GATE CHARGE (nc) QT V DS Figure. Gate To and To Voltage vs. Total Charge t, TIME (ns) V DS = V I D = A V GS = V t d(off) t f t d(on) t r I S, SOURCE CURRENT (AMPS).. V GS = V R G, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance V SD, SOURCE TO DRAIN VOLTAGE (VOLTS) Figure. Diode Forward Voltage vs. Current. ID, DRAIN CURRENT (AMPS) s ms ms SINGLE PULSE T C = C. R DS(on) LIMIT dc THERMAL LIMIT PACKAGE LIMIT... Figure. Maximum Rated Forward Biased Safe Operating Area EAS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) 7 s 7 7 I D = A T J, STARTING JUNCTION TEMPERATURE ( C) Figure. Maximum Avalanche Energy vs. Starting Junction Temperature

5 NTMS9N PACKAGE DIMENSIONS X B Y Z H G A D S C. (.) M Z Y S X S. (.) M SEATING PLANE Y. (.) M SOIC CASE 7 7 ISSUE AJ N X M K J NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.7 (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 7 6 ARE OBSOLETE. NEW STANDARD IS 7 7. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.7 BSC. BSC H.... J K M N.... S SOLDERING FOOTPRINT* STYLE :..6 PIN. SOURCE. SOURCE 3. SOURCE. GATE. DRAIN 6. DRAIN 7. DRAIN. DRAIN SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 7 USA Phone: or 3 36 Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NTMS9N/D

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