IRF3710. HEXFET Power MOSFET V DSS = 100V. R DS(on) = 23mΩ I D = 57A

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1 PD C IRF37 HEXFET Power MOSFET Advanced Process Technoogy Utra Low On-Resistance Dynamic dv/dt Rating 175 C Operating Temperature Fast Switching Fuy Avaanche Rated G D S V DSS = 0V R DS(on) = 23mΩ I D = 57A Description Advanced HEXFET Power MOSFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The TO-220 package is universay preferred for a commercia-industria appications at power dissipation eves to approximatey 50 watts. The ow therma resistance and ow package cost of the TO-220 contribute to its wide acceptance throughout the industry. TO-220AB Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain V 57 I T C = 0 C Continuous Drain V 40 A I DM Pused Drain Current 230 P C = 25 C Power Dissipation 200 W Linear Derating Factor 1.3 W/ C Gate-to-Source Votage ± 20 V I AR Avaanche Current 28 A E AR Repetitive Avaanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.8 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Sodering Temperature, for seconds 300 (1.6mm from case ) Mounting torque, 6-32 or M3 srew bf in (1.1N m) Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 R θcs Case-to-Sink, Fat, Greased Surface 0.50 C/W R θja Junction-to-Ambient /15/09

2 IRF37 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 0 V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Votage Temp. Coefficient 0.13 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 23 mω = V, I D =28A (th) Gate Threshod Votage V V DS =, I D = 250µA g fs Forward Transconductance 32 S V DS = 25V, I D = 28A I DSS Drain-to-Source Leakage Current 25 V µa DS = 0V, = 0V 250 V DS = 80V, = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 = 20V na Gate-to-Source Reverse Leakage -0 = -20V Q g Tota Gate Charge 130 I D = 28A Q gs Gate-to-Source Charge 26 nc V DS = 80V Q gd Gate-to-Drain ("Mier") Charge 43 = V, See Fig. 6 and 13 t d(on) Turn-On Deay Time 12 V DD = 50V t r Rise Time 58 I D = 28A ns t d(off) Turn-Off Deay Time 45 R G = 2.5Ω t f Fa Time 47 = V, See Fig. Between ead, L D Interna Drain Inductance 4.5 6mm (0.25in.) nh from package G L S Interna Source Inductance 7.5 and center of die contact C iss Input Capacitance 3130 = 0V C oss Output Capacitance 4 V DS = 25V C rss Reverse Transfer Capacitance 72 pf ƒ = 1.0MHz, See Fig. 5 E AS Singe Puse Avaanche Energy mj I AS = 28A, L = 0.70mH Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 57 (Body Diode) showing the A G I SM Pused Source Current integra reverse 230 (Body Diode) p-n junction diode. S V SD Diode Forward Votage 1.2 V T J = 25 C, I S = 28A, = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 28A Q rr Reverse Recovery Charge 670 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. (See fig. 11) Starting T J = 25 C, L = 0.70mH R G = 25Ω, I AS = 28A, =V (See Figure 12) ƒ I SD 28A, di/dt 380A/µs, V DD V (BR)DSS, T J 175 C Puse width 400µs; duty cyce 2%. This is a typica vaue at device destruction and represents operation outside rated imits. This is a cacuated vaue imited to T J = 175 C. D S 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRF VGS TOP 16V V 7.0V 6.0V 5.0V 4.5V 4.0V BOTTOM 3.5V 00 0 VGS TOP 16V V 7.0V 6.0V 5.0V 4.5V 4.0V BOTTOM 3.5V 3.5V 3.5V µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Votage (V) µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Votage (V) Fig 1. Typica Output Characteristics Fig 2. Typica Output Characteristics I D = 57A T J = 175 C.00 T J = 25 C 1.00 V DS = 15V 50V 20µs PULSE WIDTH , Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF), Gate-to-Source Votage (V) IRF = 0V, f = 1 MHZ C iss = C gs C gd, C ds C rss = C gd C oss = C ds C gd Ciss SHORTED I D = 28A V DS = 80V V DS = 50V V DS = 20V 00 Coss Crss V DS, Drain-to-Source Votage (V) Q G Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 175 C 0µsec.00 1msec T 1.00 J = 25 C = 0V V SD, Source-toDrain Votage (V) Tc = 25 C Tj = 175 C Singe Puse msec V DS, Drain-toSource Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 IRF37 60 V DS R D I D, Drain Current (A) T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G Puse Width 1 µs Duty Factor 0.1 % D.U.T. Fig a. Switching Time Test Circuit % t d(on) t r t d(off) t f Fig b. Switching Time Waveforms - V DD 1 Therma Response (Z thjc ) 0.1 D = SINGLE PULSE (THERMAL RESPONSE) P DM t 1 t 2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc T C t 1, Rectanguar Puse Duration (sec) Fig 11. Maximum Effective Transient Therma Impedance, Junction-to-Case 5

6 IRF37 R G V DS 20V tp Fig 12a. Uncamped Inductive Test Circuit tp L D.U.T IAS 0.01Ω 15V DRIVER V (BR)DSS - V DD A E AS, Singe Puse Avaanche Energy (mj) TOP BOTTOM Starting T, Junction Temperature ( J C) I D 11A 20A 28A Fig 12c. Maximum Avaanche Energy Vs. Drain Current I AS Fig 12b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF Q GS Q GD D.U.T. V - DS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Samping Resistors Fig 13b. Gate Charge Test Circuit 6

7 IRF37 Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Poarity of D.U.T for P-Channe Driver Gate Drive Period P.W. D = P.W. Period [ =V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Appied Votage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Rippe 5% Forward Drop [ V DD ] [ ] I SD *** = 5.0V for Logic Leve and 3V Drive Devices Fig 14. For N-channe HEXFET power MOSFETs 7

8 IRF37 TO-220AB Package Outine Dimensions are shown in miimeters (inches) TO-220AB Part Marking Information (;$03/( 7,6,6$1,5) /27&2'( $66(0%/('21::,17($66(0%/</,1(& Note: "P" in assemby ine position indicates "Lead-Free",17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$57180%(5 '$7(&2'( <($5 :((. /,1(& Note: For the most current drawing pease refer to IR website at Data and specifications subject to change without notice. This product has been designed and quaified for the Automotive [Q1] market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.09/

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