P-Channel 20 V (D-S) MOSFET

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1 Si30CDS P-Channel 0 V (D-S) MOSFET MOSFET PRODUCT SUMMARY V DS (V) R DS(on) ( ) I D (A) a Q g (Typ.) at V GS = V at V GS = -.5 V nc TO-36 (SOT-3) FEATURES Halogen-free According to IEC Definition TrenchFET Power MOSFET Compliant to RoHS Directive 00/95/EC APPLICATIONS Load Switch G 3 D S Top View Si30CDS (N)* * Marking Code Ordering Information: Si30CDS-T-E3 (Lead (Pb)-free) Si30CDS-T-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (T A = 5 C, unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage V DS - 0 V Gate-Source Voltage V GS ± 8 T C = 5 C - 3. T C = 70 C -.5 Continuous Drain Current (T J = 50 C) I D T A = 5 C -.3 b, c T A = 70 C -.8 b, c A Pulsed Drain Current I DM - 0 T C = 5 C -.3 Continuous Source-Drain Diode Current I S T A = 5 C b, c T C = 5 C.6 T C = 70 C.0 Maximum Power Dissipation P D W T A = 5 C 0.86 b, c T A = 70 C 0.55 b, c Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambient b, d 5 s R thja 0 45 C/W Maximum Junction-to-Foot (Drain) Steady State R thjf 6 78 Notes: a. Based on T C = 5 C. b. Surface mounted on " x " FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 75 C/W. Document Number: 6874 S0-430-Rev. C, 5-Oct-0

2 Si30CDS MOSFET SPECIFICATIONS (T J = 5 C, unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage V DS V GS = 0 V, I D = - 50 µa - 0 V V DS Temperature Coefficient V DS /T J - 8 I D = - 50 µa V GS(th) Temperature Coefficient V GS(th) /T J. mv/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = - 50 µa V Gate-Source Leakage I GSS V DS = 0 V, V GS = ± 8 V ± 00 na V DS = - 0 V, V GS = 0 V - Zero Gate Voltage Drain Current I DSS V DS = - 0 V, V GS = 0 V, T J = 55 C - 0 µa On-State Drain Current a I D(on) V DS - 5 V, V GS = V - 6 A Drain-Source On-State Resistance a V GS = V, I D = -.8 A R DS(on) V GS = -.5 V, I D = -.0 A Forward Transconductance a g fs V DS = - 5 V, I D = -.8 A 9.5 S Dynamic b Input Capacitance C iss 405 Output Capacitance C oss V DS = - 0 V, V GS = 0 V, f = MHz 75 pf Reverse Transfer Capacitance C rss 55 V DS = - 0 V, V GS = V, I D = - 3 A Total Gate Charge Q g nc Gate-Source Charge Q gs V DS = - 0 V, V GS = -.5 V, I D = - 3 A 0.7 Gate-Drain Charge Q gd.3 Gate Resistance R g f = MHz 6.0 Turn-On Delay Time t d(on) 0 Rise Time t r V DD = - 0 V, R L = Turn-Off Delay Time t d(off) I D = - A, V GEN = V, R g = ns Fall Time t f 0 0 Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 5 C -.3 Pulse Diode Forward Current a I SM - 0 A Body Diode Voltage V SD I S = A V Body Diode Reverse Recovery Time t rr ns Body Diode Reverse Recovery Charge Q rr 5 50 nc I F = A, di/dt = 00 A/µs, T J = 5 C Reverse Recovery Fall Time t a 5 ns Reverse Recovery Rise Time t b 5 Notes: a. Pulse test; pulse width 300 µs, duty cycle %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 6874 S0-430-Rev. C, 5-Oct-0

3 Si30CDS TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) 0 V GS =5V thru.5 V V GS =V I D - Drain Current (A) 6 4 V GS =.5V I D - Drain Current (A) T C = - 55 C T C = 5 C T C = 5 C V GS =V V DS - Drain-to-Source Voltage (V) Output Characteristics V GS - Gate-to-Source Voltage (V) Transfer Characteristics On-Resistance (Ω) R DS(on) V GS =.5V V GS =4.5V C - Capacitance (pf) C oss C iss I D - Drain Current (A) On-Resistance vs. Drain Current and Gate Voltage C rss V DS - Drain-to-Source Voltage (V) Capacitance 8.5 I D =3A I D =.8 A - Gate-to-Source Voltage (V) V GS 6 4 V DS =5V V DS =5V V DS =0V R DS(on) - On-Resistance (Normalized) V GS =4.5V V GS =.8V Q g - Total Gate Charge (nc) Gate Charge T J -Junction Temperature ( C) On-Resistance vs. Junction Temperature Document Number: 6874 S0-430-Rev. C, 5-Oct-0 3

4 Si30CDS TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) I D =.8 A - Source Current (A) IS T J = 50 C T J = 5 C T J = - 50 C R DS(on) - On-Resistance (Ω) T J = 5 C V SD -Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage 0.4 T J =5 C V GS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage I D = 50 µa 8 Variance (V) V GS(th) I D =ma Power (W) T A = 5 C T J - Temperature ( C) Threshold Voltage Time (s) Single Pulse Power 0 Limited by R DS(on) * 00 µs - Drain Current (A) I D 0. T A = 5 C Single Pulse BVDSS Limited V DS - Drain-to-Source Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area ms 0 ms 00 ms s 0 s 00 s, DC 00 4 Document Number: 6874 S0-430-Rev. C, 5-Oct-0

5 Si30CDS TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance Single Pulse Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance Single Pulse Notes: P DM t t t. Duty Cycle, D = t. Per Unit Base = R thjf =50 C/W 3. T JM -T A =P DM Z (t) thja 4. Surface Mounted Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?6874. Document Number: 6874 S0-430-Rev. C, 5-Oct-0 5

6 Package Information SOT-3 (TO-36): 3-LEAD b 3 E E S e e D A A 0.0 mm C 0.004" Seating Plane C q 0.5 mm Gauge Plane Seating Plane A C L L Dim MILLIMETERS INCHES Min Max Min Max A A A b c D E E e 0.95 BSC Ref e.90 BSC Ref L L 0.64 Ref 0.05 Ref S 0.50 Ref 0.00 Ref q ECN: S Rev. K, 09-Jul-0 DWG: 5479 Document Number: Jul-0

7 AN807 Mounting LITTLE FOOT SOT-3 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. ambient air. This pattern uses all the available area underneath the body for this purpose See Application Note 86, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs, (http:///doc?786), for the basis of the pad design for a LITTLE FOOT SOT-3 power MOSFET footprint. In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package FIGURE. Footprint With Copper Spreading The electrical connections for the SOT-3 are very simple. Pin is the gate, pin is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, thermal connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. Figure shows the footprint with copper spreading for the SOT-3 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.00 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. Document Number: Nov-03

8 Application Note 86 RECOMMENDED MINIMUM PADS FOR SOT (0.950) 0.0 (0.559) 0.09 (0.74) 0.06 (.69) (.45) (.34) (.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 7609 Revision: -Jan-08 5

9 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, Vishay ), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Vishay s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer s technical experts. Product specifications do not expand or otherwise modify Vishay s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Revision: 3-Jun-6 Document Number: 9000

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