C Soldering Temperature, for 10 seconds 300 (1.6mm from case )
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1 l dvanced Process Technology l Surface Mount (IRF5305S) l Lowprofile throughhole (IRF5305L) l 175 C Operating Temperature l Fast Switching l PChannel l Fully valanche Rated Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The throughhole version (IRF5305L) is available for lowprofile applications. G PD 91386C IRF5305S/L HEXFET Power MOSFET D S 2 D Pak TO262 V DSS = 55V R DS(on) = 0.06Ω I D = 31 bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 31 I T C = 0 C Continuous Drain Current, V V 22 I DM Pulsed Drain Current 1 P = 25 C Power Dissipation 3.8 W P C = 25 C Power Dissipation 1 W Linear Derating Factor 0.71 W/ C V GS GatetoSource Voltage ± 20 V E S Single Pulse valanche Energy 280 mj I R valanche Current 16 E R Repetitive valanche Energy 11 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.8 V/ns T J Operating Junction and 55 to T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (1.6mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase 1.4 R θj Junctiontombient ( PCB Mounted,steadystate)** 40 C/W 4/1/99
2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 55 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1m R DS(on) Static DraintoSource OnResistance 0.06 Ω V GS = V, I D = 16 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ g fs Forward Transconductance 8.0 S V DS = 25V, I D = 16 I DSS DraintoSource Leakage Current 25 V µ DS = 55V, V GS = 0V 250 V DS = 44V, V GS = 0V, T J = 150 C I GSS GatetoSource Forward Leakage 0 V GS = 20V n GatetoSource Reverse Leakage 0 V GS = 20V Q g Total Gate Charge 63 I D = 16 Q gs GatetoSource Charge 13 nc V DS = 44V Q gd GatetoDrain ("Miller") Charge 29 V GS = V, See Fig. 6 and 13 t d(on) TurnOn Delay Time 14 V DD = 28V t r Rise Time 66 I D = 16 ns t d(off) TurnOff Delay Time 39 R G = 6.8Ω t f Fall Time 63 R D = 1.6Ω, See Fig. L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 1200 V GS = 0V C oss Output Capacitance 520 pf V DS = 25V C rss Reverse Transfer Capacitance 250 ƒ = 1.0MHz, See Fig. 5 SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 31 (Body Diode) showing the I SM Pulsed Source Current integral reverse G 1 (Body Diode) pn junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 16, V GS = 0V t rr Reverse Recovery Time 71 1 ns T J = 25 C, I F = 16 Q rr Reverse Recovery Charge nc di/dt = 0/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) Pulse width 300µs; duty cycle 2%. V DD = 25V, Starting T J = 25 C, L = 2.1mH Uses IRF5305 data and test conditions R G = 25Ω, I S = 16. (See Figure 12) ƒ I SD 16, di/dt 280/µs, V DD V (BR)DSS, T J 175 C ** When mounted on 1" square PCB (FR4 or G Material ). For recommended footprint and soldering techniques refer to application note #N
3 I D, DraintoSource Current () 00 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, DraintoSource Current () 00 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 20µs PULSE WIDTH T J c= 25 C T 1 1 C J = 175 C V DS, DraintoSource Voltage (V) V DS, DraintoSource Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current () 0 T = 25 C J T = 175 C J V DS= 25V 20µs PULSE W IDTH V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics R DS(on), D raintosource O n R esistance (Normalized) I D = 27 V GS= V T J, Junction Temperature ( C) Fig 4. Normalized OnResistance Vs. Temperature 3
4 C, Capacitance (pf) V GS = 0V, f = 1MHz C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd C iss C oss C rss V, GatetoSource Voltage (V) GS I D = 16 V DS = 44V V DS = 28V V DS, DraintoSource Voltage (V) Fig 5. Typical Capacitance Vs. DraintoSource Voltage FOR TEST CIRCUIT 0 SEE FIGURE Q G, Total Gate Charge (nc) Fig 6. Typical Gate Charge Vs. GatetoSource Voltage I SD, Reverse Drain Current () 00 0 T = 175 C J T = 25 C J V GS = 0V V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage I D, Drain Current () 00 0 OPERTION IN THIS RE LIMITED BY R DS(on) 0µs 1ms T ms C = 25 C T J = 175 C Single P u lse V DS, DraintoSource Voltage (V) Fig 8. Maximum Safe Operating rea 4
5 V DS R D R G V GS D.U.T. + V DD I D, Drain Current () V Pulse Width 1 µs Duty Factor 0.1 % Fig a. Switching Time Test Circuit V GS t d(on) t r t d(off) t f % T C, Case Temperature ( C) 90% V DS Fig 9. Maximum Drain Current Vs. Case Temperature Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = SINGLE PULSE (THERML RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc + TC t 1, Rectangular Pulse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Thermal Impedance, JunctiontoCase 5
6 Fig 12a. Unclamped Inductive Test Circuit I S V DS L R G D.U.T V DD IS 20V DRIVER tp 0.01Ω 15V E S, Single Pulse valanche Energy (mj) ID TOP BOTTOM 16 V DD = 25V Starting T J, Junction Temperature ( C) Fig 12c. Maximum valanche Energy Vs. Drain Current tp V (BR)DSS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. V Q G 12V.2µF 50KΩ.3µF Q GS Q GD D.U.T. V + DS V G V GS 3m Charge I G I D Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6
7 Peak Diode Recovery dv/dt Test Circuit IRF5305S/L D.U.T* + ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer + + V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. Device Under Test + V DD * Reverse Polarity of D.U.T for PChannel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =V ] *** D.U.T. I SD Waveform Reverse Recovery Current Repplied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For PChannel HEXFETS 7
8 D 2 Pak Package Outline 1.40 (.055) M X..54 (.415).29 (.405) (.185) 4.20 (.165) B 1.32 (.052) 1.22 (.048).16 (.400) REF (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.6) (.580) 2.79 (.1) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.3) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) REF (.0) M B M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS FTER SOLDER DIP. 2 DIMENSIONING & TOLERNCING PER NSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HETSINK & LED DIMENSIONS DO NOT INCLUDE BURRS. LED SSIGNMENTS 1 GTE 2 DRIN 3 SOURCE 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.0) 2X Part Marking Information D 2 Pak INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE F530S B 1M PRT NUMBER DTE CODE (YYW W ) YY = YER WW = WEEK 8
9 Package Outline TO262 Outline Part Marking Information TO
10 Tape & Reel Information D 2 Pak TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION 1.85 (.073) 1.65 (.065) (.457) (.449) (.609) (.601) (.957) (.941) TRL.90 (.429).70 (.421) 16. (.634) (.626) 1.75 (.069) 1.25 (.049) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MX (2.362) MIN. NOTES : 1. COMFORMS TO EI CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLNGE OUTER EDGE (1.039) (.961) (1.197) MX. 4 WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) IR GRET BRITIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CND: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) IR GERMNY: Saalburgstrasse 157, Bad Homburg Tel: IR ITLY: Via Liguria 49, 071 Borgaro, Torino Tel: IR FR EST: K&H Bldg., 2F, 304 NishiIkebukuro 3Chome, ToshimaKu, Tokyo Japan 171 Tel: IR SOUTHEST SI: 1 Kim Seng Promenade, Great World City West Tower, 1311, Singapore Tel: IR TIWN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673, Taiwan Tel: Data and specifications subject to change without notice. 4/99
11 Note: For the most current drawings please refer to the IR website at:
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