IRLR8743PbF IRLU8743PbF HEXFET Power MOSFET

Transcription

1 Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l Lead-Free Benefits l Very Low RDS(on) at 4.5V V GS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current PD IRLR8743PbF IRLU8743PbF HEXFET Power MOSFET V DSS R DS(on) max Qg 30V 3.m: 39nC D G S D-Pak IRLR8743PbF G DS I-Pak IRLU8743PbF Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 I T C = 25 C Continuous Drain Current, V 0V 60f I T C = C Continuous Drain Current, V 0V 3f A I DM Pulsed Drain Current c 640 P C = 25 C Maximum Power Dissipation g 35 W P C = C Maximum Power Dissipation g 68 Linear Derating Factor 0.90 W/ C T J Operating Junction and -55 to 75 C T STG Storage Temperature Range Soldering Temperature, for 0 seconds 300 (.6mm from case) Thermal Resistance G D S Gate Drain Source Parameter Typ. Max. Units R θjc Junction-to-Case. R θja Junction-to-Ambient (PCB Mount) g 50 C/W R θja Junction-to-Ambient 0 Notes through are on page 08/5/07

2 IRLR/U8743PbF T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 20 mv/ C R DS(on) Static Drain-to-Source On-Resistance mω V GS = 4.5V, I D = 20A e V GS(th) Gate Threshold Voltage V V DS = V GS, I D = µa V GS(th) / T J Gate Threshold Voltage Coefficient -6.4 mv/ C I DSS Drain-to-Source Leakage Current.0 V DS = 24V, V GS = 0V µa 50 V DS = 24V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage V GS = 20V na Gate-to-Source Reverse Leakage - V GS = -20V gfs Forward Transconductance 89 S V DS = 5V, I D = 20A Q g Total Gate Charge Q gs Pre-Vth Gate-to-Source Charge 0 V DS = 5V Q gs2 Post-Vth Gate-to-Source Charge 3.9 nc V GS = 4.5V Q gd Gate-to-Drain Charge 3 I D = 20A Q godr Gate Charge Overdrive 2 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 7 Q oss Output Charge 2 nc V DS = 6V, V GS = 0V R G Gate Resistance Ω t d(on) Turn-On Delay Time 9 V DD = 5V, V GS = 4.5Ve t r Rise Time 35 I D = 20A ns t d(off) Turn-Off Delay Time 2 R G =.8Ω t f Fall Time 7 See Fig. 4 C iss Input Capacitance 4880 V GS = 0V C oss Output Capacitance 950 pf V DS = 5V C rss Reverse Transfer Capacitance 470 ƒ =.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 250 mj I AR Avalanche Currentc 20 A E AR Repetitive Avalanche Energy c 3.5 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = ma V GS = 0V, I D = 25A e Conditions I S Continuous Source Current MOSFET symbol 60f (Body Diode) showing the A I SM Pulsed Source Current integral reverse 640 (Body Diode)c p-n junction diode. V SD Diode Forward Voltage.0 V T J = 25 C, I S = 20A, V GS = 0V e t rr Reverse Recovery Time 8 27 ns T J = 25 C, I F = 20A, V DD = 5V Q rr Reverse Recovery Charge nc di/dt = 300A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2

3 I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRLR/U8743PbF VGS TOP 0V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V VGS TOP 0V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 0 2.5V 60µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 0 2.5V 60µs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 I D = 25A V GS = 0V.5 0 T J = 75 C 0. T J = 25 C V DS = 5V 60µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRLR/U8743PbF 00 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 20A V DS = 24V V DS = 5V 0 C iss C oss C rss.0 0 V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 0 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 75 C µsec T J = 25 C msec 0 0msec 0 V GS = 0V V SD, Source-to-Drain Voltage (V) 0. Tc = 25 C Tj = 75 C Single Pulse 0 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) V GS(th), Gate Threshold Voltage (V) IRLR/U8743PbF Limited By Package I D = µa T C, Case Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 0. Threshold Voltage vs. Temperature 0 Thermal Response ( Z thjc ) C/W D = SINGLE PULSE ( THERMAL RESPONSE ) τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri R R 2 R 3 R R 2 R 3 Ri ( C/W) τi (sec) R 4 R Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc 0.00 E-006 E t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 τ 4 τ 4 τ C τ

6 E AS, Single Pulse Avalanche Energy (mj) IRLR/U8743PbF 5V 200 R G V DS 20V V GS tp L D.U.T IAS 0.0Ω DRIVER - V DD A I D TOP 2.7A 3.7A BOTTOM 20A Fig 2a. Unclamped Inductive Test Circuit 400 tp V (BR)DSS Starting T J, Junction Temperature ( C) Fig 2c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms V DS R D R G V GS D.U.T. - V DD Current Regulator Same Type as D.U.T. V GS 50KΩ Pulse Width µs Duty Factor 0. % 2V.2µF.3µF Fig 4a. Switching Time Test Circuit D.U.T. V - DS V DS 90% V GS 3mA I G I D Current Sampling Resistors 0% V GS t d(on) t r t d(off) t f Fig 3. Gate Charge Test Circuit Fig 4b. Switching Time Waveforms 6

7 IRLR/U8743PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =0V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 5. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Id Vds Vgs Vgs(th) Qgodr Qgd Qgs2 Qgs Fig 6. Gate Charge Waveform 7

8 IRLR/U8743PbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q2. Power losses in the high side switch Q, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f I Q gs 2 V in f i g ( ) Q g V g f Q oss 2 V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs2, can be seen from Fig 6. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. i g Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V in f Q rr V in f *dissipated primarily in Q. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8

9 IRLR/U8743PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information (;$03/( 7,6,6$,5)5 :,7$66(0%/< $66(0%/('2::,7($66(0%/</,($ RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/<,5)5 $ 3$5780%(5 '$7(&2'( <($5 :((. /,($ 3LQDVVHPEO\OLQHSRVLWLRQLQGLFDWHV /HDG)UHHTXDOLILFDWLRQWRWKHFRQVXPHUOHYHO 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/<,5)5 3$5780%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ 3 '(6,*$7(6/($')5(( 352'8&748$/,),('727( &2680(5/(9(/237,2$/ <($5 :((. $ $66(0%/<6,7(&2'( Note: For the most current drawing please refer to IR website at 9

10 IRLR/U8743PbF I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-25AA) Part Marking Information (;$03/( 7,6,6$,5)8 :,7$66(0%/< $66(0%/('2::,7($66(0%/</,($ RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/<,5)8 $ 3$5780%(5 '$7(&2'( <($5 :((. /,($ 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/<,5)8 3$5780%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ <($5 :((. $ $66(0%/<6,7(&2'( Note: For the most current drawing please refer to IR website at 0

11 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR IRLR/U8743PbF TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA INCH NOTES :. OUTLINE CONFORMS TO EIA mm Note: Notes: For the most current drawing please refer to IR website at Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L =.252mH, R G = 25Ω, I AS = 20A. ƒ Pulse width 400µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 50A. When mounted on " square PCB (FR-4 or G-0 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) Visit us at for sales contact information.08/2007