IRFR3707Z IRFU3707Z HEXFET Power MOSFET

Transcription

1 Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Benefits l l l Very Low R DS(on) at 4.5V V GS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current PD IRFR3707Z IRFU3707Z HEXFET Power MOSFET V DSS R DS(on) max Qg 30V 9.5m: 9.6nC D-Pak IRFR3707Z I-Pak IRFU3707Z Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 I T C = 25 C Continuous Drain Current, V 10V 56f A I T C = 100 C Continuous Drain Current, V 10V 39f I DM Pulsed Drain Current c 220 P C = 25 C Maximum Power Dissipation 50 W P C = 100 C Maximum Power Dissipation Linear Derating Factor W/ C T J Operating Junction and -55 to 175 C T STG Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 3.0 C/W R θja Junction-to-Ambient (PCB Mount) g 50 R θja Junction-to-Ambient 110 Notes through are on page /03/03

2 IRFR/U3707Z T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance mω V GS = 10V, I D = 15A e V GS = 4.5V, I D = 12A e V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA V GS(th) / T J Gate Threshold Voltage Coefficient -5.0 mv/ C I DSS Drain-to-Source Leakage Current 1.0 µa V DS = 24V, V GS = 0V 150 V DS = 24V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 100 na V GS = 20V Gate-to-Source Reverse Leakage -100 V GS = -20V gfs Forward Transconductance 71 S V DS = 15V, I D = 12A Q g Total Gate Charge Q gs1 Pre-Vth Gate-to-Source Charge 2.6 V DS = 15V Q gs2 Post-Vth Gate-to-Source Charge 0.90 nc V GS = 4.5V Q gd Gate-to-Drain Charge 3.5 I D = 12A Q godr Gate Charge Overdrive 2.6 See Fig. 16 Q sw Switch Charge (Q gs2 Q gd ) 4.4 Q oss Output Charge 5.8 nc V DS = 15V, V GS = 0V t d(on) Turn-On Delay Time 8.0 V DD = 16V, V GS = 4.5V e t r Rise Time 11 I D = 12A t d(off) Turn-Off Delay Time 12 ns Clamped Inductive Load t f Fall Time 3.3 C iss Input Capacitance 1150 V GS = 0V C oss Output Capacitance 260 pf V DS = 15V C rss Reverse Transfer Capacitance 120 ƒ = 1.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 42 mj I AR Avalanche Currentc 12 A E AR Repetitive Avalanche Energy c 5.0 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 56f Conditions V GS = 0V, I D = 250µA Conditions MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 220 integral reverse G S (Body Diode)c p-n junction diode. V SD Diode Forward Voltage 1.0 V T J = 25 C, I S = 12A, V GS = 0V e t rr Reverse Recovery Time ns T J = 25 C, I F = 12A, V DD = 15V Q rr Reverse Recovery Charge nc di/dt = 100A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2 D

3 I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFR/U3707Z VGS TOP 10V 6.0V 4.5V 4.0V 3.3V 2.8V 2.5V BOTTOM 2.2V VGS TOP 10V 6.0V 4.5V 4.0V 3.3V 2.8V 2.5V BOTTOM 2.2V V 20µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) V 20µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics T J = 175 C 2.0 I D = 30A V GS = 10V T J = 25 C V DS = 10V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRFR/U3707Z V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 12A V DS = 24V V DS = 15V C iss 3.0 C oss 2.0 C rss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 175 C µsec T 1.00 J = 25 C V GS = 0V V SD, Source-to-Drain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse 1msec 10msec V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) V GS(th) Gate threshold Voltage (V) IRFR/U3707Z Limited By Package I D = 250µA T C, Case Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 10 Thermal Response ( Z thjc ) D = SINGLE PULSE ( THERMAL RESPONSE ) R 1 R 2 R 3 R 1 R 2 R 3 τ J τ J τ 1 τ τ 2 τ 3 1 τ 2 τ 3 Ci= τi/ri Ci= τi/ri 1E-006 1E t 1, Rectangular Pulse Duration (sec) τ C τ Ri ( C/W) τi (sec) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 E AS, Single Pulse Avalanche Energy (mj) IRFR/U3707Z R G V DS 20V V GS tp L D.U.T I AS 0.01Ω 15V DRIVER - V DD A Fig 12a. Unclamped Inductive Test Circuit I D TOP 3.7A 5.6A BOTTOM 12A tp V (BR)DSS Starting T J, Junction Temperature ( C) Fig 12c. Maximum Avalanche Energy vs. Drain Current I AS L D Fig 12b. Unclamped Inductive Waveforms V DS V DD - Current Regulator Same Type as D.U.T. 50KΩ V GS Pulse Width < 1µs Duty Factor < 0.1% D.U.T 12V.2µF.3µF D.U.T. V - DS Fig 14a. Switching Time Test Circuit V DS 90% V GS 3mA I G I D Current Sampling Resistors 10% V GS Fig 13. Gate Charge Test Circuit t d(on) t r t d(off) t f Fig 14b. Switching Time Waveforms 6

7 IRFR/U3707Z - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =10V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform 7

8 IRFR/U3707Z Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f i g ( ) Q g V g f Q oss 2 V f in I Q gs2 i g V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs1 and Q gs2, can be seen from Fig 16. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 Rds(on) ( ) Q g V g f Q oss 2 V in f Q rr V in f *dissipated primarily in Q1. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q1 turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8

9 IRFR/U3707Z D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 6.73 (.265) 6.35 (.250) - A (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) (.040) 1.64 (.025) 1.52 (.060) 1.15 (.045) 2X 1.14 (.045) 0.76 (.030) X 6.22 (.245) 5.97 (.235) - B (.035) 0.64 (.025) 0.25 (.010) M A M B (.410) 9.40 (.370) 6.45 (.245) 5.68 (.224) 0.51 (.020) MIN (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 2.28 (.090) 4.57 (.180) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.006). D-Pak (TO-252AA) Part Marking Information Notes: This part marking information applies to devices produced before 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P INTERNATIONAL RECTIFIER LOGO IRFU U 1P DATE CODE YEAR = 0 WE EK = 16 AS S E MBL Y LOT CODE Notes: This part marking information applies to devices produced after 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A 9

10 IRFR/U3707Z I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 1.52 (.060) 1.15 (.045) 6.73 (.265) 6.35 (.250) - A (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN B (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.006). 3X 1.14 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.010) M A M B 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) I-Pak (TO-251AA) Part Marking Information Notes : This part marking information applies to devices produced before 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P INTERNATIONAL RECTIFIER LOGO IRFU U 1P DATE CODE YEAR = 0 WEEK = 16 AS S E MBLY LOT CODE Notes: This part marking information applies to devices produced after 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 5678 ASS EMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 19 LINE A 10

11 IRFR/U3707Z D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA INCH NOTES : 1. OUTLINE CONFORMS TO EIA mm Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.58mH, R G = 25Ω, I AS = 12A. ƒ Pulse width 400µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information. 03/

12 Note: For the most current drawings please refer to the IR website at: