Features. Symbol JEDEC TO-220AB

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1 Data Sheet June 1999 File Number A, 5V,.4 Ohm, N-Channel Power MOSFET This is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Formerly developmental type TA9771. Ordering Information PART NUMBER PACKAGE BRAND BUZ11 TO-22AB BUZ11 NOTE: When ordering, use the entire part number. Features 3A, 5V r DS(ON) =.4Ω SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Majority Carrier Device Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol D G S Packaging JEDEC TO-22AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. or Copyright Intersil Corporation 1999

2 Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified BUZ11 UNITS Drain to Source Breakdown Voltage (Note 1) V Drain to Gate Voltage (R GS = 2kΩ) (Note 1) V DGR 5 V Continuous Drain Current T C = 3 o C I D 3 A Pulsed Drain Current (Note 3) I DM 12 A Gate to Source Voltage V GS ±2 V Maximum Power Dissipation P D 75 W Linear Derating Factor W/ o C Operating and Storage Temperature T J, T STG -55 to 15 o C DIN Humidity Category - DIN E IEC Climatic Category - DIN IEC /15/56 Maximum Temperature for Soldering Leads at.63in (1.6mm) from Case for 1s T L 3 Package Body for 1s, See Techbrief T pkg 26 CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25 o C to 125 o C. BUZ11 o C o C Electrical Specifications T C = 25 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BS I D = 25µA, V GS = V V Gate Threshold Voltage V GS(TH) V GS =, I D = 1mA (Figure 9) V Zero Gate Voltage Drain Current I DSS T J = 25 o C, = 5V, V GS = V µa T J = 125 o C, = 5V, V GS = V µa Gate to Source Leakage Current I GSS V GS = 2V, = V na Drain to Source On Resistance (Note 2) r DS(ON) I D = 15A, V GS = 1V (Figure 8) Ω Forward Transconductance (Note 2) g fs = 25V, I D = 15A (Figure 11) S Turn-On Delay Time t d(on) V CC = 3V, I D 3A, V GS = 1V, R GS = 5Ω, ns Rise Time t r R L = 1Ω ns Turn-Off Delay Time t d(off) ns Fall Time t f ns Input Capacitance C ISS = 25V, V GS = V, f = 1MHz (Figure 1) pf Output Capacitance C OSS pf Reverse Transfer Capacitance C RSS pf Thermal Resistance Junction to Case R θjc 1.67 o C/W Thermal Resistance Junction to Ambient R θja 75 o C/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Continuous Source to Drain Current I SD T C = 25 o C A Pulsed Source to Drain Current I SDM T C = 25 o C A Source to Drain Diode Voltage V SD T J = 25 o C, I SD = 6A, V GS = V V Reverse Recovery Time t rr T J = 25 o C, I SD = 3A, di SD /dt = 1A/µs, ns Reverse Recovery Charge Q RR V R = 3V µc NOTES: 2. Pulse Test: Pulse width 3ms, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4-6

3 Typical Performance Curves Unless Otherwise Specified V GS > 1V POWER DISSIPATION MULTIPLIER T A, CASE TEMPERATURE ( o C) T C, CASE TEMPERATURE ( o C) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE Z θjc, TRANSIENT THERMAL IMPEDANCE P DM t 1 SINGLE PULSE NOTES: t 2 DUTY FACTOR: D = t 1 /t 2 PEAK T J = P DM x Z θjc + T C t, RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON), DRAIN TO SOURCE VOLTAGE (V) 2.5µs 1µs 1µs 1ms T C = 25 o C 1ms T J = MAX RATED 1ms SINGLE PULSE DC P D = 75W V GS = 2V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX 1V V GS = 8.V V GS = 7.5V V GS = 7.V V GS = 6.5V V GS = 6.V V GS = 5.5V V GS = 5.V V GS = 4.5V V GS = 4.V , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 4-7

4 Typical Performance Curves Unless Otherwise Specified (Continued) I DS(ON), DRAIN TO SOURCE CURRENT (A) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX = 25V V GS, GATE TO SOURCE VOLTAGE (V) r DS(ON), ON-STATE RESISTANCE (Ω) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = 5V 5.5V 6V 6.5V 7V 7.5V 8V 9V 1V 2V FIGURE 6. TRANSFER CHARACTERISTICS FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT r DS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX I D = 15A, V GS = 1V T J, JUNCTION TEMPERATURE ( o C) V GS(TH), GATE THRESHOLD VOLTAGE (V) = V GS I D = 1mA T J, JUNCTION TEMPERATURE ( o C) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 9. GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE C, CAPACITANCE (nf) C ISS C OSS C RSS 1-1 V GS = V, f = 1MHz C ISS = C GS + C GD C RSS = C GD C OSS C DS + C GD , DRAIN TO SOURCE VOLTAGE (V) FIGURE 1. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE g fs, TRANSCONDUCTANCE (S) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX = 25V T J = 25 o C FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT 4-8

5 Typical Performance Curves Unless Otherwise Specified (Continued) I SD, SOURCE TO DRAIN CURRENT (A) 1 3 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX T J = 25 o C 1 2 T J = 15 o C V SD, SOURCE TO DRAIN VOLTAGE (V) V GS, GATE TO SOURCE VOLTAGE (V) 15 I D = 45A = 1V 1 = 4V Q g, GATE CHARGE (nc) FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms t ON t d(on) t OFF t d(off) R L t r t f 9% 9% + R G V DD - 1% 1% DUT 9% V GS V GS 1% 5% PULSE WIDTH 5% FIGURE 14. SWITCHING TIME TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR (ISOLATED SUPPLY) V DD 12V BATTERY.2µF 5kΩ.3µF SAME TYPE AS DUT Q gs Q gd Q g(tot) V GS D G DUT I g(ref) I G CURRENT SAMPLING RESISTOR S I D CURRENT SAMPLING RESISTOR I g(ref) FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS 4-9

6 All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop Melbourne, FL 3292 TEL: (47) FAX: (47) For information regarding Intersil Corporation and its products, see web site EUROPE Intersil SA Mercure Center 1, Rue de la Fusee 113 Brussels, Belgium TEL: (32) FAX: (32) ASIA Intersil (Taiwan) Ltd. 7F-6, No. 11 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) FAX: (886)

7 This datasheet has been downloaded from: Datasheets for electronic components.

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