SMPS MOSFET. V DSS Rds(on) max I D
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1 pplications l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching SMPS MOSFET PD 9880 IRFP460 HEXFET Power MOSFET V DSS Rds(on) max I D 500V 0.27Ω 20 Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, valanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and valanche Voltage and Current l Effective Coss specified ( See N0) TO247C G D S bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 20 I T C = 0 C Continuous Drain Current, V V 3 I DM Pulsed Drain Current 80 P C = 25 C Power Dissipation 280 W Linear Derating Factor 2.2 W/ C V GS GatetoSource Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 3.8 V/ns T J Operating Junction and 55 to 50 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torqe, 632 or M3 screw lbf in (.N m) Typical SMPS Topologies: l Full Bridge l PFC Boost Notes through are on page 8 6/23/99
2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 500 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.6 V/ C Reference to 25 C, I D = m R DS(on) Static DraintoSource OnResistance 0.27 Ω V GS = V, I D = 2 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ 25 V µ DS = 500V, V GS = 0V I DSS DraintoSource Leakage Current 250 V DS = 400V, V GS = 0V, T J = 25 C GatetoSource Forward Leakage 0 V GS = 30V I GSS n GatetoSource Reverse Leakage 0 V GS = 30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance S V DS = 50V, I D = 2 Q g Total Gate Charge 5 I D = 20 Q gs GatetoSource Charge 26 nc V DS = 400V Q gd GatetoDrain ("Miller") Charge 42 V GS = V, See Fig. 6 and 3 t d(on) TurnOn Delay Time 8 V DD = 250V t r Rise Time 55 ns I D = 20 t d(off) TurnOff Delay Time 45 R G = 4.3Ω t f Fall Time 39 R D = 3Ω,See Fig. C iss Input Capacitance 30 V GS = 0V C oss Output Capacitance 480 V DS = 25V C rss Reverse Transfer Capacitance 8 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 4430 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 30 V GS = 0V, V DS = 400V, ƒ =.0MHz C oss eff. Effective Output Capacitance 40 V GS = 0V, V DS = 0V to 400V valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energy 960 mj I R valanche Current 20 E R Repetitive valanche Energy 28 mj Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase 0.45 R θcs CasetoSink, Flat, Greased Surface 0.24 C/W R θj Junctiontombient 40 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 20 (Body Diode) showing the G I SM Pulsed Source Current integral reverse 80 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.8 V T J = 25 C, I S = 20, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 20 Q rr Reverse RecoveryCharge µc di/dt = 0/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) 2
3 I D, DraintoSource Current () 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, DraintoSource Current () 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C V DS, DraintoSource Voltage (V) 20µs PULSE WIDTH T J = 50 C 0 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current () 0 T J = 50 C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) I D = 9 20 V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature 3
4 C, Capacitance (pf) V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss C oss C rss 0 00 V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) I = D 9 20 V DS = 400V V DS = 250V V DS = 0V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage 0 00 OPERTION IN THIS RE LIMITED BY R DS(on) I SD, Reverse Drain Current () T J = 50 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Voltage (V) I D, Drain Current () 0 us 0us ms TC = 25 C TJ = 50 C Single Pulse ms V DS, DraintoSource Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating rea 4
5 20 V DS R D I D, Drain Current () 5 5 Fig a. Switching Time Test Circuit V DS 90% R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase 5
6 Fig 2a. Unclamped Inductive Test Circuit I S R G V DS 20V tp tp L D.U.T I S 0.0Ω V (BR)DSS Fig 2b. Unclamped Inductive Waveforms Q G 5V DRIVER V DD E S, Single Pulse valanche Energy (mj) TOP BOTTOM I D Starting T, Junction Temperature( J C) Fig 2c. Maximum valanche Energy Vs. Drain Current V Q GS Q GD 620 V G 2V V GS Current Regulator Same Type as D.U.T..2µF 50KΩ 3m.3µF Charge Fig 3a. Basic Gate Charge Waveform D.U.T. V DS V DSav, valanche Voltage (V) I av, valanche Current () I G I D Current Sampling Resistors Fig 2d. Typical DraintoSource Voltage Fig 3b. Gate Charge Test Circuit Vs. valanche Current 6
7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Repplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For NChannel HEXFETS 7
8 Package Outline TO247C Outline Dimensions are shown in millimeters (inches) 5.90 (.626) 5.30 (.602) B 3.65 (.43) 3.55 (.40) 0.25 (.0) M 5.50 (.27) D B M D 5.30 (.209) 4.70 (.85) 2.50 (.089).50 (.059) (.800) 9.70 (.775) 4.80 (.583) 4.20 (.559) 2 3 2X C 4.30 (.70) 3.70 (.45) 5.50 (.27) 4.50 (.77) NOTES: DIMENSIONING & TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO247C (.094) 2.00 (.079) 2X 5.45 (.25) 2X Part Marking Information TO247C EXMPLE :.40 (.056) 3X.00 (.039) 0.25 (.0) M C S 3.40 (.33) 3.00 (.8) THIS IS N IRFPE30 W ITH SSEMBLY LO T CO D E 3Q Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 4.3mH R G = 25Ω, I S = 20. (See Figure 2) ƒ I SD 20, di/dt 25/µs, V DD V (BR)DSS, T J 50 C INTERNTIONL RECTIFIER LO G O SSEMBLY LO T CO D E 0.80 (.03) 3X 0.40 (.06) 2.60 (.2) 2.20 (.087) IRFPE30 3Q 9302 Pulse width 300µs; duty cycle 2%. LED SSIGNMENTS GTE 2 DRIN 3 SOURCE 4 DRIN PRT NUMBER DTE CODE (YYW W ) YY = YER WW WEEK C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) IR GRET BRITIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CND: 5 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) IR GERMNY: Saalburgstrasse 57, 6350 Bad Homburg Tel: IR ITLY: Via Liguria 49, 07 Borgaro, Torino Tel: IR FR EST: K&H Bldg., 2F, 304 NishiIkebukuro 3Chome, ToshimaKu, Tokyo Japan 7 Tel: IR SOUTHEST SI: Kim Seng Promenade, Great World City West Tower, 3, Singapore Tel: IR TIWN:6 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673, Taiwan Tel: Data and specifications subject to change without notice. 6/99 8
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