C Soldering Temperature, for 10 seconds 300 (1.6mm from case )

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1 dvanced Process Technology Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fully valanche Rated Lead-Free Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. G PD IRF520NPbF HEXFET Power MOSFET D S TO-220B V DSS = 00V R DS(on) = 0.20Ω I D = 9.7 bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 0V 9.7 I T C = 00 C Continuous Drain Current, V 0V 6.8 I DM Pulsed Drain Current 38 P C = 25 C Power Dissipation 48 W Linear Derating Factor 0.32 W/ C V GS Gate-to-Source Voltage ± 20 V E S Single Pulse valanche Energy2 9 mj I R valanche Current 5.7 E R Repetitive valanche Energy 4.8 mj dv/dt Peak Diode Recovery dv/dt V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 srew 0 lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 3. R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θj Junction-to-mbient 62 /5/03

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 00 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0. V/ C Reference to 25 C, I D = m R DS(on) Static Drain-to-Source On-Resistance 0.20 Ω V GS = 0V, I D = V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ g fs Forward Transconductance 2.7 S V DS = 50V, I D = 5.7 I DSS Drain-to-Source Leakage Current 25 V µ DS = 00V, V GS = 0V 250 V DS = 80V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 00 V GS = 20V n Gate-to-Source Reverse Leakage -00 V GS = -20V Q g Total Gate Charge 25 I D = 5.7 Q gs Gate-to-Source Charge 4.8 nc V DS = 80V Q gd Gate-to-Drain ("Miller") Charge V GS = 0V, See Fig. 6 and 3 4 t d(on) Turn-On Delay Time 4.5 V DD = 50V t r Rise Time 23 I D = 5.7 ns t d(off) Turn-Off Delay Time 32 R G = 22Ω t f Fall Time 23 R D = 8.6Ω, See Fig. 0 4 Between lead, L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact C iss Input Capacitance 330 V GS = 0V C oss Output Capacitance 92 pf V DS = 25V C rss Reverse Transfer Capacitance 54 ƒ =.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol 9.7 (Body Diode) showing the G I SM Pulsed Source Current integral reverse 38 (Body Diode) p-n junction diode. V SD Diode Forward Voltage.3 V T J = 25 C, I S = 5.7, V GS = 0V 4 t rr Reverse Recovery Time ns T J = 25 C, I F = 5.7 Q rr Reverse RecoveryCharge nc di/dt = 00/µs 4 D S Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) 2 V DD = 25V, starting T J = 25 C, L = 4.7mH R G = 25Ω, I S = 5.7. (See Figure 2) 3 I SD 5.7, di/dt 240/µs, V DD V (BR)DSS, T J 75 C 4 Pulse width 300µs; duty cycle 2%.

3 I, Drain-to-Source Current () D 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T C = 25 C V DS, Drain-to-Source Voltage (V) I, Drain-to-Source Current () D 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T C = 75 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J T = 75 C J V DS= 50V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) I = 9.5 D V GS = 0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature

4 C, Capacitance (pf) 600 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd 500 C oss = C ds Cgd C iss C oss 200 C rss V DS, Drain-to-Source Voltage (V) V, Gate-to-Source Voltage (V) GS I = 5.7 D V DS = 80V V DS = 50V V DS = 20V FOR TEST CIRCUIT SEE FIGURE Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J I D, Drain Current () 00 0 OPERTION IN THIS RE LIMITED BY RDS(on) 0µs 00µs ms 0ms V GS = 0V V SD, Source-to-Drain Voltage (V) T C = 25 C T J = 75 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea

5 V DS R D R G V GS D.U.T. - V DD I D, Drain Current () Fig 0a. Switching Time Test Circuit V DS 90% 0V Pulse Width µs Duty Factor 0. % T C, Case Temperature ( C) 0% V GS t d(on) t r t d(off) t f Fig 9. Maximum Drain Current Vs. Case Temperature Fig 0b. Switching Time Waveforms 0 Thermal Response (Z thjc ) 0. D = SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 L V DS D.U.T. R G V - DD 0 V I S t p 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS t p V DD V DS E S, Single Pulse valanche Energy (mj) I D TOP BOTTOM 5.7 V DD = 25V Starting T J, Junction Temperature ( C) I S Fig 2b. Unclamped Inductive Waveforms Fig 2c. Maximum valanche Energy Vs. Drain Current Current Regulator Same Type as D.U.T. 50KΩ 0 V Q GS Q G Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3m Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D.U.T 3 - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-pplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS

8 TO-220B Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) (.255) 6.0 (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LED SSIGNMENTS LED SSIGNMENTS HEXFET IGBTs, CoPCK - GTE - GTE 2 - DRIN - GTE 2- DRIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRIN 3- EMITTER 4- DRIN 4- COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.00) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.04) DIMENSIONING & TOLERNCING PER NSI Y4.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO-220B. 2 CONTROLLING DIMENSION : INCH 4 HETSINK & LED MESUREMENTS DO NOT INCLUDE BURRS. TO-220B Part Marking Information EXMPLE: THIS IS N IRF00 LOT CODE 789 SSEMBLED ON WW 9, 997 IN THE SSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE PRT NUMBER DTE CODE YER 7 = 997 WEEK 9 LINE C Data and specifications subject to change without notice. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (30) TC Fax: (30) Visit us at for sales contact information./03

9 Note: For the most current drawings please refer to the IR website at:

10 Mouser Electronics uthorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: International Rectifier: IRF520NPBF

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