IRLR8256PbF IRLU8256PbF HEXFET Power MOSFET

Transcription

1 Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Benefits l Very Low RDS(on) at 4.5V V GS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current l Lead-Free l RoHS compliant PD A IRLR8256PbF IRLU8256PbF HEXFET Power MOSFET V DSS R DS(on) max Qg 25V 5.7m: nc D G S D-Pak IRLR8256PbF G DS I-Pak IRLU8256PbF G D S Gate Drain Source Absolute Maximum Ratings V DS V GS I T C = 25 C I T C = 0 C I DM P C = 25 C P C = 0 C T J T STG Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, V V Continuous Drain Current, V V Pulsed Drain Current c Maximum Power Dissipation g Maximum Power Dissipation g Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for seconds Max. 25 ± 20 8f 57f to (.6mm from case) Units V A W W/ C C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case h 2.4 R θja Junction-to-Ambient (PCB Mount) g 50 R θja Junction-to-Ambient C/W ORDERING INFORMATION: See detailed ordering and shipping information on the last page of this data sheet. Notes through are on page 08/02/

2 IRLR/U8256PbF T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions BV DSS Drain-to-Source Breakdown Voltage 25 V V GS = 0V, I D = 250μA ΔΒV DSS /ΔT J Breakdown Voltage Temp. Coefficient 8 mv/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance V GS = V, I D = 25A e mω V GS = 4.5V, I D = 20A e V GS(th) Gate Threshold Voltage V V ΔV GS(th) /ΔT DS = V GS, I D = 25μA J Gate Threshold Voltage Coefficient -7.2 mv/ C I DSS Drain-to-Source Leakage Current.0 V DS = 20V, V GS = 0V μa 50 V DS = 20V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 0 V GS = 20V na Gate-to-Source Reverse Leakage -0 V GS = -20V gfs Forward Transconductance 8 S V DS = 3V, I D = 20A Q g Total Gate Charge 5 Q gs Pre-Vth Gate-to-Source Charge 2.3 Q gs2 Post-Vth Gate-to-Source Charge.6 nc Q gd Gate-to-Drain Charge 3.6 Q godr Gate Charge Overdrive 2.6 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 5. Q oss Output Charge 9.0 nc R G Gate Resistance Ω t d(on) Turn-On Delay Time 9.7 t r Rise Time 46 t d(off) Turn-Off Delay Time 2 t f Fall Time 8.5 C iss Input Capacitance 470 C oss Output Capacitance 453 C rss Reverse Transfer Capacitance 85 Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 86 mj I AR Avalanche Currentc 20 A E AR Repetitive Avalanche Energy c 6.3 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 8f (Body Diode) A I SM Pulsed Source Current 325 (Body Diode)c V SD Diode Forward Voltage.0 V t rr Reverse Recovery Time 9 29 ns Q rr Reverse Recovery Charge 7 26 nc V DS = 3V V GS = 4.5V I D = 20A V DS = 6V, V GS = 0V V DD = 3V, V GS = 4.5Ve I D = 20A R G =.8Ω See Fig. 4 V GS = 0V V DS = 3V ƒ =.0MHz Conditions MOSFET symbol showing the integral reverse p-n junction diode. T J = 25 C, I S = 20A, V GS = 0V e T J = 25 C, I F = 20A, V DD = 3V di/dt = 250A/μs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2 ns pf

3 I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRLR/U8256PbF 00 0 VGS TOP V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 00 0 VGS TOP V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 2.5V 2.5V 60μs PULSE WIDTHTj = 25 C V DS, Drain-to-Source Voltage (V) 60μs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 25A V GS = V 0 T J = 75 C.5 0. T J = 25 C V DS = 5V 60μs PULSE WIDTH V GS, Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRLR/U8256PbF 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 20A V DS = 20V V DS = 3V C iss C oss 2.0 C rss V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) 0 T J = 75 C 0 msec 0μsec msec T J = 25 C V GS = 0V V SD, Source-to-Drain Voltage (V) Tc = 25 C Tj = 75 C Single Pulse 0 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 V GS(th), I D, Drain Current (A) Gate threshold Voltage (V) IRLR/U8256PbF Limited By Package I D = 25μA T C, Case Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Threshold Voltage vs. Temperature Thermal Response ( Z thjc ) C/W D = SINGLE PULSE ( THERMAL RESPONSE ) τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri R R 2 R 3 R R 2 R 3 R 4 Ri ( C/W) τi (sec) R Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc 0.00 E-006 E t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 τ 4 τ 4 τ C τ

6 E AS, Single Pulse Avalanche Energy (mj) IRLR/U8256PbF 5V 400 V DS L DRIVER I D TOP 5.57A 8.50A BOTTOM 20A R G 20V V GS tp D.U.T IAS 0.0Ω - V DD A Fig 2a. Unclamped Inductive Test Circuit 50 0 tp V (BR)DSS Starting T J, Junction Temperature ( C) Fig 2c. Maximum Avalanche Energy vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms V DS R D R G V GS D.U.T. - V DD Current Regulator Same Type as D.U.T. V GS 50KΩ Pulse Width µs Duty Factor 0. % 2V.2μF.3μF Fig 4a. Switching Time Test Circuit D.U.T. V - DS V DS 90% V GS 3mA I G I D Current Sampling Resistors % V GS t d(on) t r t d(off) t f Fig 3. Gate Charge Test Circuit Fig 4b. Switching Time Waveforms 6

7 IRLR/U8256PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 5. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Id Vds Vgs Vgs(th) Qgodr Qgd Qgs2 Qgs Fig 6. Gate Charge Waveform 7

8 IRLR/U8256PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 234 ASSEMBLED ON WW 6, 200 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" "P" in assembly line position indicates "Lead-Free" qualification to the consumer-level INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE IRFR20 6A 2 34 PART NUMBER DATE CODE YEAR = 200 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE IRFR PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) P = DESIGNATES LEAD-FREE PRODUCT QUALIFIED TO THE CONSUMER LEVEL (OPTIONAL) YEAR = 200 WEEK 6 A = ASSEMBLY SITE CODE Note: For the most current drawing please refer to IR website at 8

9 I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) IRLR/U8256PbF I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU20 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 200 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 9A PART NUMBER DATE CODE YEAR = 200 WEEK 9 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR = 200 WEEK 9 A = ASSEMBLY SITE CODE Note: For the most current drawing please refer to IR website at 9

10 IRLR/U8256PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA INCH NOTES :. OUTLINE CONFORMS TO EIA mm Note: For the most current drawing please refer to IR website at

11 IRLR/U8256PbF Orderable part number Package Type Standard Pack Form Quantity IRLR8256PBF D-PAK Tube/Bulk 75 IRLR8256TRPBF D-PAK Tape and Reel 2000 Note IRLR8256PBF I-PAK Tube/Bulk 75 Qualification Information Qualification level Moisture Sensitivity Level RoHS Compliant (per JEDEC JESD47F guidelines) Comments: This family of products has passed JEDEC s Industrial qualification. IR s Consumer qualification level is granted by extension of the higher Industrial level. MSL D-PAK (per JEDEC J-STD-020D ) I-PAK Industrial Yes Not applicable Qualification standards can be found at International Rectifier s web site Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information: Applicable version of JEDEC standard at the time of product release. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.43mH, R G = 25Ω, I AS = 20A. ƒ Pulse width 400μs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 50A. When mounted on " square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. R θ is measured at T J approximately 90 C. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: N.Sepulveda blvd, El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.08/20