C Soldering Temperature, for 10 seconds 300 (1.6mm from case )

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1 l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Fully Avalanche Rated l Optimized for SMPS Applications Description Advanced HEXFET Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G IRFZ44V HEXFET Power MOSFET D S PD B V DSS = 60V R DS(on) = 6.5mΩ I D = 55A The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 55 I T C = 0 C Continuous Drain Current, V V 39 A I DM Pulsed Drain Current 220 P C = 25 C Power Dissipation 5 W Linear Derating Factor 0.77 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 5 mj I AR Avalanche Current 55 A E AR Repetitive Avalanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 4.5 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 srew lbf in (.N m) Thermal Resistance TO-220AB Parameter Typ. Max. Units R θjc Junction-to-Case.3 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 /29/03

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 60 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 6.5 mω V GS = V, I D = 3A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA g fs Forward Transconductance 24 S V DS = 25V, I D = 3A I DSS Drain-to-Source Leakage Current 25 V µa DS = 60V, V GS = 0V 250 V DS = 48V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 20V na Gate-to-Source Reverse Leakage -0 V GS = -20V Q g Total Gate Charge 67 I D = 5A Q gs Gate-to-Source Charge 8 nc V DS = 48V Q gd Gate-to-Drain ("Miller") Charge 25 V GS = V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 3 V DD = 30V t r Rise Time 97 I D = 5A ns t d(off) Turn-Off Delay Time 40 R G = 9.Ω t f Fall Time 57 R D = 0.6Ω, See Fig. Between lead, L D Internal Drain Inductance 4 5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7 5 and center of die contact C iss Input Capacitance 82 V GS = 0V C oss Output Capacitance 393 V DS = 25V C rss Reverse Transfer Capacitance 3 pf ƒ =.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 55 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 220 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 2.5 V T J = 25 C, I S = 5A, V GS = 0V t rr Reverse Recovery Time 70 5 ns T J = 25 C, I F = 5A Q rr Reverse Recovery Charge nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 89µH R G = 25Ω, I AS = 5A. (See Figure 2) ƒ I SD 5A, di/dt 227A/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. 2

3 I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V 20µs PULSE WIDTH T J = 25 C V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig Typical Output Characteristics Fig 2 Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 25 C T J = 75 C V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 55A V GS = V T J, Junction Temperature ( C) Fig 3 Typical Transfer Characteristics Fig 4 Normalized On-Resistance Vs Temperature 3

4 C, Capacitance(pF) IRFZ44V V GS = 0V, f = MHZ C is = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss V GS, Gate-to-Source Voltage (V) I D = 5A V DS= 48V V DS= 30V V DS= 2V 0 Crss 0 V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5 Typical Capacitance Vs Drain-to-Source Voltage Fig 6 Typical Gate Charge Vs Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J= 75 C T J= 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms TC = 25 C ms TJ = 75 C Single Pulse 0 00 V DS, Drain-to-Source Voltage (V) Fig 7 Typical Source-Drain Diode Forward Voltage Fig 8 Maximum Safe Operating Area 4

5 60 V DS R D I D, Drain Current (A) V GS D U T R G V Pulse Width µs Duty Factor 0. % Fig a Switching Time Test Circuit V DS 90% V - DD T C, Case Temperature ( C) % V GS t d(on) t r t d(off) t f Fig 9 Maximum Drain Current Vs Case Temperature Fig b Switching Time Waveforms Thermal Response(Z thjc ) 0. D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t Peak T J=P DMx Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 5V V DS L DRIVER R G 20V D.U.T IAS - V DD A tp 0.0Ω Fig 2a Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 2A 36A 5A Starting T, Junction Temperature ( J C) Fig 2c Maximum Avalanche Energy Vs Drain Current I AS Fig 2b Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF V Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 3a Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D U T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D U T I SD controlled by Duty Factor "D" D U T - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4 For N-Channel HEXFETS 7

8 Package Outline TO-220AB Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) - A (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) (.255) 6. (.240) (.045) MIN LEAD ASSIGNMENTS - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 4.09 (.555) 3.47 (.530) 4.06 (.60) 3.55 (.40) 3X.40 (.055).5 (.045) 2.54 (.0) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) DIMENSIONING & TOLERANCING PER ANSI Y4.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. Part Marking Information TO-220AB EXAMPLE : THIS IS AN IRF WITH ASSEMBLY LOT CODE 9BM INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRF B M A PART NUMBER DATE CODE (YYWW) YY = YEAR WW = WEEK Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. /03 8

9 Note: For the most current drawings please refer to the IR website at:

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