N-channel enhancement mode TrenchMOS transistor

Transcription

1 FEATURES SYMBOL QUICK REFERENCE DATA Trench technology d V DSS = V Low on-state resistance Fast switching I D = A High thermal cycling performance Low thermal resistance R DS(ON) mω (V GS = V) g s R DS(ON) mω (V GS =. V) GENERAL DESCRIPTION PINNING SOT PIN DESCRIPTION field-effect transistor in a plastic envelope using trench gate technology. drain Applications:- Motor and relay drivers source d.c. to d.c. converters Logic level translator drain (tab) The is supplied in the SOT surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC ) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DSS Drain-source voltage T j = C to C - V V DGR Drain-gate voltage T j = C to C; R GS = kω - V V GS Gate-source voltage - ± V I D Continuous drain current T sp = C - A T sp = C -. A T amb = C -. A I DM Pulsed drain current T sp = C - A P D Total power dissipation T sp = C - 8. W T j, T stg Operating junction and - C storage temperature THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-sp Thermal resistance junction to surface mounted, FR K/W solder point board R th j-amb Thermal resistance junction to surface mounted, FR - K/W ambient board Continuous current rating limited by package February Rev.

2 AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC ) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT E AS Non-repetitive avalanche Unclamped inductive load, I AS = A; - mj energy t p =. ms; T j prior to avalanche = C; V DD V; R GS = Ω; V GS = V I AS Non-repetitive avalanche - A current ELECTRICAL CHARACTERISTICS T j = C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = V; I D = µa; - - V voltage T j = - C - - V V GS(TO) Gate threshold voltage V DS = V GS ; I D = ma.8 V T j = C. - - V T j = - C -. V R DS(ON) Drain-source on-state V GS = V; I D =. A - 8 mω resistance V GS =. V; I D = A - mω V GS = V; I D =. A; T j = C - - mω g fs Forward transconductance V DS = V; I D =. A. - S I D(ON) On-state drain current V GS = V; V DS = V;. - - A V GS =. V; V DS = V - - A I DSS Zero gate voltage drain V DS = V; V GS = V; - na current V DS = V; V GS = V; T j = C -. µa I GSS Gate source leakage current V GS = ± V; V DS = V - na Q g(tot) Total gate charge I D =. A; V DD = V; V GS = V - - nc Q gs Gate-source charge -. - nc Q gd Gate-drain (Miller) charge -. - nc t d on Turn-on delay time V DD = V; R D = 8 Ω; - - ns t r Turn-on rise time V GS = V; R G = Ω ns t d off Turn-off delay time Resistive load - - ns t f Turn-off fall time - - ns L d Internal drain inductance Measured tab to centre of die -. - nh L s Internal source inductance Measured from source lead to source - - nh bond pad C iss Input capacitance V GS = V; V DS = V; f = MHz - - pf C oss Output capacitance pf C rss Feedback capacitance - - pf February Rev.

3 REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T j = C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I S Continuous source current T sp = C - - A (body diode) I SM Pulsed source current (body - - A diode) V SD Diode forward voltage I F =. A; V GS = V -.8. V t rr Reverse recovery time I F =. A; -di F /dt = A/µs; - - ns Q rr Reverse recovery charge V GS = V; V R = V - - nc 8 PD% Normalised Power Derating 8 Tsp / C Fig.. Normalised power dissipation. PD% = P D /P D C = f(t sp ). Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID d.c. tp = us us ms ms ms Drain-Source Voltage, VDS (V) Fig.. Safe operating area. T sp = C I D & I DM = f(v DS ); I DM single pulse; parameter t p 8 ID% Normalised Current Derating 8 Tsp / C Fig.. Normalised continuous drain current. ID% = I D /I D C = f(t sp ); conditions: V GS V.. Peak Pulsed Drain Current, IDM (A) D =..... single pulse Fig.. Transient thermal impedance. Z th j-sp = f(t); parameter D = t p /T E- E- E- E- E- E- E+ E+ Pulse width, tp (s) P D tp T D = tp/t February Rev.

4 8 Drain Current, ID (A) Tj = C VGS = V V. V. V. V Drain-Source Voltage, VDS (V) Fig.. Typical output characteristics, T j = C. I D = f(v DS ); parameter V GS V. V V.8 V Transconductance, gfs (S) Tj = C C 8 Drain current, ID (A) Fig.8. Typical transconductance, T j = C. g fs = f(i D ) ; parameter T j.. Drain-Source On Resistance, RDS(on) (Ohms). V. V.8V V. V. V Tj = C a. SOT V Trench Normalised RDS(ON) = f(tj).. VGS = V. V V 8 Drain Current, ID (A) Fig.. Typical on-state resistance, T j = C. R DS(ON) = f(i D ); parameter V GS. - Tj / C Fig.. Normalised drain-source on-state resistance. a = R DS(ON) /R DS(ON) C = f(t j ) 8 Drain current, ID (A) VDS > ID X RDS(ON) Tj = C C Gate-source voltage, VGS (V) Fig.. Typical transfer characteristics. I D = f(v GS ); parameter T j VGS(TO) / V max. typ. min Tj / C Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = ma; V DS = V GS February Rev.

5 E- E- E- E- E- min E- Fig.. Sub-threshold drain current. I D = f(v GS) ; conditions: T j = C; V DS = V GS typ Sub-Threshold Conduction max 8 Source-Drain Diode Current, IF (A) VGS = V C Tj = C Drain-Source Voltage, VSDS (V) Fig.. Typical reverse diode current. I F = f(v SDS ); conditions: V GS = V; parameter T j Capacitances, Ciss, Coss, Crss (pf) Non-repetitive Avalanche current, IAS (A) C Ciss Tj prior to avalanche = C Coss Crss VDS ID tp. Drain-Source Voltage, VDS (V) Fig.. Typical capacitances, C iss, C oss, C rss. C = f(v DS ); conditions: V GS = V; f = MHz. E- E- E- E- E- Avalanche time, tp (s) Fig.. Maximum permissible non-repetitive avalanche current (I AS ) versus avalanche time (t p ); unclamped inductive load 8 Gate-source voltage, VGS (V) ID =.A Tj = C VDD = V 8 Gate charge, QG (nc) Fig.. Typical turn-on gate-charge characteristics. V GS = f(q G ); parameter V DS February Rev.

6 PRINTED CIRCUIT BOARD Dimensions in mm. 8.. Fig.. PCB for thermal resistance and power rating for SOT. PCB: FR epoxy glass (. mm thick), copper laminate ( µm thick). February Rev.

7 MECHANICAL DATA Plastic surface mounted package; collector pad for good heat transfer; leads SOT D B E A X c y H E v M A b Q A A L p e b p w M B detail X e mm scale DIMENSIONS (mm are the original dimensions) UNIT A A b p b c D E e e H E L p Q v w y mm OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT Fig.. SOT surface mounting package. Notes. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling.. Refer to Discrete Semiconductor Packages, Data Handbook SC8.. Epoxy meets UL V at /8". February Rev.

8 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC ). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. February 8 Rev.