V DSS. 40V R DS(on) typ. 1.1m max. 1.4m 259Ac. I D (Silicon Limited) I D (Package Limited) 100A. HEXFET Power MOSFET
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1 R DS(on), Drain-to -Source On Resistance (m ) I D, Drain Current (A) Applications l Brushed Motor drive applications l BLDC Motor drive applications l Battery powered circuits l Half-bridge and full-bridge topologies l Synchronous rectifier applications l Resonant mode power supplies l OR-ing and redundant power switches l DC/DC and AC/DC converters l DC/AC Inverters PD StrongIRFET IRFH74PbF HEXFET Power MOSFET V DSS 4V R DS(on) typ. 1.1m max. 1.4m 259Ac I D (Silicon Limited) I D (Package Limited) A Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l RoHS Compliant containing no Lead, no Bromide, and no Halogen PQFN 5X6 mm Ordering Information Orderable part number Package Type Standard Pack Form Quantity IRFH74TRPBF PQFN 5mm x 6mm Tape and Reel 4 IRFH74TR2PBF PQFN 5mm x 6mm Tape and Reel 4 Note 6. I D = A Limited By Package T J = 125 C V GS, Gate -to -Source Voltage (V) Fig 1. Typical On-Resistance vs. Gate Voltage T C, Case Temperature ( C) Fig 2. Maximum Drain Current vs. Case Temperature 1 5/7/12 5
2 IRFH74PbF Absolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V V (Silicon Limited) 259c I T C = C Continuous Drain Current, V V (Silicon Limited) 164c I T C = 25 C Continuous Drain Current, V V (Wire Bond Limited) A I DM Pulsed Drain Current d 1247 P C = 25 C Maximum Power Dissipation 156 W Linear Derating Factor 1.3 W/ C V GS Gate-to-Source Voltage ± 2 V T J Operating Junction and -55 to 15 Storage Temperature Range C T STG Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 191 mj E AS (tested) Single Pulse Avalanche Energy Tested Value l 314 I AR Avalanche Currentd See Fig. 14, 15, 22a, 22b A E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R JC (Bottom) Junction-to-Case k.8 R JC (Top) Junction-to-Case k 15 R JA Junction-to-Ambient j 34 R JA (<s) Junction-to-Ambient j 21 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 4 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.33 V/ C R DS(on) Static Drain-to-Source On-Resistance m 1.7 m V GS(th) Gate Threshold Voltage V I DSS Drain-to-Source Leakage Current 1. μa 15 I GSS Gate-to-Source Forward Leakage na Gate-to-Source Reverse Leakage - R G Internal Gate Resistance 2.4 C/W Conditions V GS = V, I D = 25μA Reference to 25 C, I D = 1.mA d V GS = V, I D = A g V GS = 6.V, I D = 5A g V DS = V GS, I D = 15μA V DS = 4V, V GS = V V DS = 4V, V GS = V, T J = 125 C V GS = 2V V GS = -2V Notes: Calculated continuous current based on maximum allowable junction temperature. Package is limited to A by production test capability. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-114) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L =.38mH R G = 5, I AS = A, V GS =V. I SD A, di/dt 1366A/μs, V DD V (BR)DSS, T J 15 C. Pulse width 4μs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. ˆ When mounted on 1 inch square 2 oz copper pad on 1.5 x 1.5 in. board of FR-4 material. R is measured at T J approximately 9 C. Š This value determined from sample failure population, starting, L=.38mH, R G = 5, I AS = A, V GS =V. 2
3 IRFH74PbF (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 117 S Q g Total Gate Charge nc Q gs Gate-to-Source Charge 34 Q gd Gate-to-Drain ("Miller") Charge 4 Q sync Total Gate Charge Sync. (Q g - Q gd ) 169 t d(on) Turn-On Delay Time 15 ns t r Rise Time 51 t d(off) Turn-Off Delay Time 73 t f Fall Time 49 C iss Input Capacitance 6419 pf C oss Output Capacitance 952 C rss Reverse Transfer Capacitance 656 C oss eff. (ER) Effective Output Capacitance (Energy Related) 1161 C oss eff. (TR) Effective Output Capacitance (Time Related) 135 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current c A Conditions V DS = V, I D = A I D = A V DS =2V V GS = V g I D = A, V DS =V, V GS = V V DD = 2V I D = 3A R G = 2.7 V GS = V g V GS = V V DS = 25V ƒ = 1. MHz V GS = V, V DS = V to 32V i V GS = V, V DS = V to 32V h Conditions MOSFET symbol (Body Diode) showing the G I SM Pulsed Source Current 1247 A integral reverse (Body Diode)d p-n junction diode. S V SD Diode Forward Voltage V, I S = A, V GS = V g dv/dt Peak Diode Recovery f 2.5 V/ns T J = 175 C, I S = A, V DS = 4V t rr Reverse Recovery Time 35 ns V R = 34V, 35 T J = 125 C I F = A Q rr Reverse Recovery Charge 26 nc di/dt = A/μs g 27 T J = 125 C I RRM Reverse Recovery Current 1.5 A D 3
4 C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFH74PbF VGS TOP 15V V 8.V 7.V 6.V 5.V 4.5V BOTTOM 4.25V VGS TOP 15V V 8.V 7.V 6.V 5.V 4.5V BOTTOM 4.25V 4.25V 1. 6μs PULSE WIDTH 4.25V Tj = 25 C V DS, Drain-to-Source Voltage (V) Fig 3. Typical Output Characteristics T J = 15 C V DS = V 6μs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Fig 5. Typical Transfer Characteristics Fig 4. Typical Output Characteristics I D = A V GS = V 6μs PULSE WIDTH Tj = 15 C V DS, Drain-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 6. Normalized On-Resistance vs. Temperature C iss V GS = V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C oss I D = A V DS = 32V V DS = 2V C rss V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 7. Typical Capacitance vs. Drain-to-Source Voltage Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage 4
5 V (BR)DSS, Drain-to-Source Breakdown Voltage (V) Energy (μj) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) IRFH74PbF T J = 15 C OPERATION IN THIS AREA LIMITED BY R DS (on) μsec V GS = V V SD, Source-to-Drain Voltage (V) Fig 9. Typical Source-Drain Diode Forward Voltage Id = 1.mA 1 Tc = 25 C DC Tj = 15 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig. Maximum Safe Operating Area 1..8 Limited by pakcage V DS = V to 32V msec 1msec T J, Temperature ( C ) Fig 11. Drain-to-Source Breakdown Voltage V DS, Drain-to-Source Voltage (V) Fig 12. Typical C OSS Stored Energy R DS (on), Drain-to -Source On Resistance (m ) 4 3 V GS = 5.V V GS = 6.V V GS = 7.V V GS = 8.V V GS =V I D, Drain Current (A) Fig 13. Typical On-Resistance vs. Drain Current 5
6 E AR, Avalanche Energy (mj) Avalanche Current (A) IRFH74PbF 1 Thermal Response ( Z thjc ) C/W D = SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc.1 1E-6 1E t 1, Rectangular Pulse Duration (sec) Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 125 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25 C and Tstart = 125 C. 1 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 tav (sec) Fig 15. Typical Avalanche Current vs.pulsewidth TOP Single Pulse BOTTOM 1.% Duty Cycle I D = A Notes on Repetitive Avalanche Curves, Figures 14, 15: (For further info, see AN-5 at 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 14, 15). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 13) Starting T J, Junction Temperature ( C) Fig 16. Maximum Avalanche Energy vs. Temperature P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc I av = 2DT/ [1.3 BV Z th ] E AS (AR) = P D (ave) t av 6
7 Q RR (nc) I RRM (A) Q RR (nc) V GS(th), Gate threshold Voltage (V) I RRM (A) IRFH74PbF 4. I F = 6A 8 V R = 34V 3. 6 T J = 125 C 2. I D = 15μA I D = 1.mA I D = 1.A T J, Temperature ( C ) di F /dt (A/μs) Fig 17. Threshold Voltage vs. Temperature Fig Typical Recovery Current vs. di f /dt I F = A 3 I F = 6A 8 V R = 34V 25 V R = 34V 6 T J = 125 C 2 T J = 125 C di F /dt (A/μs) Fig Typical Recovery Current vs. di f /dt di F /dt (A/μs) Fig. 2 - Typical Stored Charge vs. di f /dt I F = A V R = 34V T J = 125 C di F /dt (A/μs) Fig Typical Stored Charge vs. di f /dt 7
8 IRFH74PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 15V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.1 - V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G - V DD VV GS Pulse Width µs Duty Factor % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5K Vgs 12V.2 F.3 F V GS D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 8
9 IRFH74PbF PQFN 5x6 Outline "B" Package Details For footprint and stencil design recommendations, please refer to application note AN-1154 at PQFN 5x6 Outline "B" Part Marking INTERNATIONAL RECTIFIER LOGO DATE CODE ASSEMBLY SITE CODE (Per SCOP 2-2) PIN 1 IDENTIFIER XXXX XYWWX XXXXX PART NUMBER ( 4 or 5 digits ) MARKING CODE (Per Marking Spec) LOT CODE (Eng Mode - Min last 4 digits of EATI#) (Prod Mode - 4 digits of SPN code) Note: For the most current drawing please refer to IR website at: 9
10 IRFH74PbF PQFN 5x6 Outline "B" Tape and Reel Note: For the most current drawing please refer to IR website at: Qualification level Moisture Sensitivity Level RoHS compliant Qualification information Industrial (per JE DE C JE S D47F guidelines ) MS L1 PQFN 5mm x 6mm (per JE DE C J-S TD-2D ) Yes Qualification standards can be found at International Rectifier s web site: Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information: Applicable version of JEDEC standard at the time of product release. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 1 N. Sepulveda Blvd., El Segundo, California 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. 5/212
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