V DSS R DS(on) typ. Trr typ. I D

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1 Applications Zero Voltage Switching SMPS Telecom and Server Power Supplies Uninterruptible Power Supplies Motor Control applications Lead-Free SMPS MOSFET PD HEXFET Power MOSFET V DSS R DS(on) typ. Trr typ. I D 600V 20mΩ 70ns 38A Features and Benefits SuperFast body diode eliminates the need for external diodes in ZVS applications. Lower Gate charge results in simpler drive requirements. Enhanced dv/dt capabilities offer improved ruggedness. Higher Gate voltage threshold offers improved noise immunity. SUPER TO-247AC Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 38 I T C = 0 C Continuous Drain Current, V V 24 A I DM Pulsed Drain Current c 50 P C = 25 C Power Dissipation 540 W Linear Derating Factor 4.3 W/ C V GS Gate-to-Source Voltage ±30 V dv/dt Peak Diode Recovery dv/dt d 3 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 screw.() N m (lbf in) Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 38 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 50 integral reverse (Body Diode)c p-n junction diode. V SD Diode Forward Voltage.5 V T J = 25 C, I S = 38A, V GS = 0V f t rr Reverse Recovery Time ns T J = 25 C, I F = 38A T J = 25 C, di/dt = 0A/µs f Q rr Reverse Recovery Charge nc T J = 25 C, I S = 38A, V GS = 0V f T J = 25 C, di/dt = 0A/µs f I RRM Reverse Recovery Current 9. 4 A T J = 25 C t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) G D S 9//04

2 T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 600 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.4 V/ C R DS(on) Static Drain-to-Source On-Resistance mω V GS(th) Gate Threshold Voltage V I DSS Drain-to-Source Leakage Current 50 µa 2.0 ma I GSS Gate-to-Source Forward Leakage 0 na Gate-to-Source Reverse Leakage -0 R G Internal Gate Resistance.2 Ω T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 20 S Q g Total Gate Charge 320 Q gs Gate-to-Source Charge 85 nc Q gd Gate-to-Drain ("Miller") Charge 60 t d(on) Turn-On Delay Time 44 t r Rise Time 30 ns t d(off) Turn-Off Delay Time 92 t f Fall Time 69 C iss Input Capacitance 7990 C oss Output Capacitance 740 C rss Reverse Transfer Capacitance 72 pf C oss eff. Effective Output Capacitance 350 C oss eff. (ER) Effective Output Capacitance 260 (Energy Related) Avalanche Characteristics Symbol Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 680 mj I AR Avalanche Currentc 38 A E AR Repetitive Avalanche Energy c 54 mj Thermal Resistance Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = ma V GS = V, I D = 23A f V DS = V GS, I D = 250µA V DS = 600V, V GS = 0V V DS = 480V, V GS = 0V, T J = 25 C V GS = 30V V GS = -30V f = MHz, open drain Conditions V DS = 50V, I D = 23A I D = 38A V DS = 480V V GS = V, See Fig. 7 & 5 f V DD = 300V I D = 38A R G = 4.3Ω V GS = V, See Fig. a & b f V GS = 0V V DS = 25V ƒ =.0MHz, See Fig. 5 V GS = 0V,V DS = 0V to 480V g Symbol Parameter Typ. Max. Units R θjc Junction-to-Case 0.22 R θcs Case-to-Sink, Flat, Greased Surface 0.24 C/W R θja Junction-to-Ambient 40 Notes: Repetitive rating; pulse width limited by Pulse width 300µs; duty cycle 2%. max. junction temperature. (See Fig. ) C oss eff. is a fixed capacitance that gives the same charging time Starting T J = 25 C, L = 0.9mH, R G = 25Ω, as C oss while V DS is rising from 0 to 80% V DSS. I AS = 38A, dv/dt = 3V/ns. (See Figure 2a) C oss eff.(er) is a fixed capacitance that stores the same energy ƒ I SD 38A, di/dt 630A/µs, V DD V (BR)DSS, as C oss while V DS is rising from 0 to 80% V DSS. T J 50 C. 2

3 I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V V µs PULSE WIDTH Tj = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 0. 20µs PULSE WIDTH Tj = 50 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 00 0 T J = 50 C I D = 38A V GS = V T J = 25 C V GS, Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 V GS, Gate-to-Source Voltage (V) I SD, Reverse Drain Current (A) C, Capacitance(pF) Energy (µj) V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typ. Output Capacitance Stored Energy vs. V DS I D = 38A V DS = 480V V DS = 300V V DS = 20V T J = 50 C Q G Total Gate Charge (nc) T.00 J = 25 C V GS = 0V V SD, Source-to-Drain Voltage (V) Fig 7. Typical Gate Charge vs. Fig 8. Typical Source-Drain Diode Gate-to-Source Voltage Forward Voltage 4

5 I D, Drain-to-Source Current (A) I D, Drain Current (A) 00 OPERATION IN THIS AREA LIMITED BY R DS (on) µsec msec Tc = 25 C Tj = 50 C Single Pulse msec V DS, Drain-to-Source Voltage (V) T C, Case Temperature ( C) Fig 9. Maximum Safe Operating Area Fig. Maximum Drain Current vs. Case Temperature R G V GS V V DS Pulse Width µs Duty Factor 0. % R D D.U.T. - V DD V DS 90% % V GS t d(on) t r t d(off) t f Fig a. Switching Time Test Circuit Fig b. Switching Time Waveforms 5

6 V GS(th) Gate threshold Voltage (V) Thermal Response ( Z thjc ) D = P DM SINGLE PULSE ( THERMAL RESPONSE ) E-006 E Notes: t, Rectangular Pulse Duration (sec). Duty factor D = t / t 2 t 2. Peak T J = P DM x Z thjc T C t 2 Fig 2. Maximum Effective Transient Thermal Impedance, Junction-to-Case I D = 250µA T J, Temperature ( C ) Fig 3. Threshold Voltage vs. Temperature 6

7 E AS, Single Pulse Avalanche Energy (mj) I D TOP 7A 24A BOTTOM 38A Starting T J, Junction Temperature ( C) Fig 4a. Maximum Avalanche Energy vs. Drain Current 5V V (BR)DSS V DS L DRIVER tp R G 20V tp D.U.T I AS 0.0Ω - V DD A I AS Fig 4b. Unclamped Inductive Test Circuit Current Regulator Same Type as D.U.T. Fig 4c. Unclamped Inductive Waveforms 2V.2µF 50KΩ.3µF D.U.T. V - DS V GS V Q GS Q G Q GD V GS V G 3mA I G I D Current Sampling Resistors Fig 5a. Gate Charge Test Circuit Charge Fig 5b. Basic Gate Charge Waveform 7

8 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 6. For N-Channel HEXFET Power MOSFETs 8

9 Case Outline and Dimensions Super-247 Super-247 (TO-274AA) Part Marking Information EXAMPLE: THIS IS AN IRFPS37N50A W ITH ASSEM BLY LO T CO DE 789 ASSEM BLED O N W W 9, 997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER L O G O IR FPS 37N 50A 7 79C 89 PART NUMBER ASSEMBLY LOT CODE N o te : "P " in a s s e m b ly lin e p o s itio n indicates "Lead-Free" TOP DATE CODE (YYW W ) YY = YEAR W W = W E E K Super TO-247AC package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.09/04 9

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