Chapter 3. Sequential Logic Design. Copyright 2013 Elsevier Inc. All rights reserved.
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1 Chapter 3 Sequential Logic Design 1
2 Figure 3.1 Cross-coupled inverter pair 2
3 Figure 3.2 Bistable operation of cross-coupled inverters 3
4 Figure 3.3 SR latch schematic 4
5 Figure 3.4 Bistable states of SR latch 5
6 Figure 3.5 SR latch truth table 6
7 Figure 3.6 SR latch symbol 7
8 Figure 3.7 D latch: (a) schematic, (b) truth table, (c) symbol 8
9 Figure 3.8 D flip-flop: (a) schematic, (b) symbol, (c) condensed symbol 9
10 Figure 3.9 A 4-bit register: (a) schematic and (b) symbol 10
11 Figure 3.10 Enabled flip-flop: (a, b) schematics, (c) symbol 11
12 Figure 3.11 Synchronously resettable flip-flop: (a) schematic, (b, c) symbols 12
13 Figure 3.12 D latch schematic 13
14 Figure 3.13 D flip-flop schematic 14
15 Figure 3.14 Example waveforms 15
16 Figure 3.15 Solution waveforms 16
17 Figure 3.16 Three-inverter loop 17
18 Figure 3.17 Ring oscillator waveforms 18
19 Figure 3.18 An improved (?) D latch 19
20 Figure 3.19 Latch waveforms illustrating race condition 20
21 Figure 3.20 Flip-flop current state and next state 21
22 Figure 3.21 Example circuits 22
23 Figure 3.22 Finite state machines: (a) Moore machine, (b) Mealy machine 23
24 Figure 3.23 Campus map 24
25 Figure 3.24 Black box view of finite state machine 25
26 Figure 3.25 State transition diagram 26
27 Figure 3.26 State machine circuit for traffic light controller 27
28 Figure 3.27 Timing diagram for traffic light controller 28
29 Figure 3.28 Divide-by-3 counter (a) waveform and (b) state transition diagram 29
30 Figure 3.29 Divide-by-3 circuits for (a) binary and (b) one-hot encodings 30
31 Figure 3.30 FSM state transition diagrams: (a) Moore machine, (b) Mealy machine 31
32 Figure 3.31 FSM schematics for (a) Moore and (b) Mealy machines 32
33 Figure 3.32 Timing diagrams for Moore and Mealy machines 33
34 Figure 3.33 (a) single and (b) factored designs for modified traffic light controller FSM 34
35 Figure 3.34 State transition diagrams: (a) unfactored, (b) factored 35
36 Figure 3.35 Circuit of found FSM for Example
37 Figure 3.36 State transition diagram of found FSM from Example
38 Figure 3.37 Timing specification for synchronous sequential circuit 38
39 Figure 3.38 Path between registers and timing diagram 39
40 Figure 3.39 Maximum delay for setup time constraint 40
41 Figure 3.40 Minimum delay for hold time constraint 41
42 Figure 3.41 Back-to-back flip-flops 42
43 Figure 3.42 Sample circuit for timing analysis 43
44 Figure 3.43 Timing diagram: (a) general case, (b) critical path, (c) short path 44
45 Figure 3.44 Corrected circuit to fix hold time problem 45
46 Figure 3.45 Timing diagram with buffers to fix hold time problem 46
47 Figure 3.46 Clock skew caused by wire delay 47
48 Figure 3.47 Timing diagram with clock skew 48
49 Figure 3.48 Setup time constraint with clock skew 49
50 Figure 3.49 Hold time constraint with clock skew 50
51 Figure 3.50 Input changing before, after, or during aperture 51
52 Figure 3.51 Stable and metastable states 52
53 Figure 3.52 Synchronizer symbol 53
54 Figure 3.53 Simple synchronizer 54
55 Figure 3.54 Input timing 55
56 Figure 3.55 Circuit model of bistable device 56
57 Figure 3.56 Resolution trajectories 57
58 Figure 3.57 Spatial and temporal parallelism in the cookie kitchen 58
59 Figure 3.58 Circuit with no pipelining 59
60 Figure 3.59 Circuit with two-stage pipeline 60
61 Figure 3.60 Circuit with three-stage pipeline 61
62 Figure 3.61 Input waveforms of SR latch for Exercise
63 Figure 3.62 Input waveforms of SR latch for Exercise
64 Figure 3.63 Input waveforms of D latch or flip-flop for Exercises 3.3 and
65 Figure 3.64 Input waveforms of D latch or flip-flop for Exercises 3.4 and
66 Figure 3.65 Mystery circuit 66
67 Figure 3.66 Mystery circuit 67
68 Figure 3.67 Muller C-element 68
69 Figure 3.68 Circuits 69
70 Figure 3.69 State transition diagram 70
71 Figure 3.70 State transition diagram 71
72 Figure 3.71 FSM input waveforms 72
73 Figure 3.72 FSM schematic 73
74 Figure 3.73 FSM schematic 74
75 Figure 3.74 Registered four-input XOR circuit 75
76 Figure bit adder schematic 76
77 Figure 3.76 New and improved synchronizer 77
78 Figure 3.77 Signal waveforms 78
79 Figure M 01 79
80 Figure M 02 80
81 Figure M 03 81
82 Figure M 04 82
83 Figure M 05 83
84 UNN Figure 1 84
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