Digital Fundamentals

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1 igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Summary Latches (biestables) A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory. The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAN gates. With NOR gates, the latch responds to active-high inputs; with NAN gates, it responds to active-low inputs. S R Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved

2 Funcionamiento S-R Summary The active-high S-R latch is in a stable (latched) condition when both inputs are LOW. Assume the latch is initially RESET ( = 0) and the inputs are at their inactive level (0). To SET the latch ( = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. To RESET the latch ( = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. 0 R 10 Latch initially RESET 01 0 S 0 0 R S Latch initially SET Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Funcionamiento S -R Summary The active-low S-R latch is in a stable (latched) condition when both inputs are HIGH. Assume the latch is initially RESET ( = 0) and the inputs are at their inactive level (1). To SET the latch ( = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. To RESET the latch a momentary LOW is applied to the R input while S is HIGH. Never apply an active set and reset at the same time (invalid). 1 S 10 Latch initially RESET 01 1 R 1 S 1 R 01 Latch initially 10 SET Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved

3 Símbolos lógicos Tabla de verdad del S -R Funcionamiento de un S -R

4 Otra forma de expresar la tabla de verdad del S -R Tabla de verdad del S-R

5 Latch S-R con puerta (entrada de habilitación) Tabla de verdad

6 Latch Memoriza el bit en la entrada : será igual a cuando la entrada EN está activa. Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Otra forma de expresar la tabla de verdad Funcionamiento en el tiempo

7 Flip-flops Summary A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked (sincronizado) device, in which only the clock edge determines when a new bit is entered. The active edge can be positive or negative. C C ynamic input indicator (a) Positive edge-triggered (b) Negative edge-triggered Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Flip flops sincronizados por flanco de subida y de bajada

8 Funcionamiento de un flip-flop S-R sincronizado por flanco de subida

9 Un flip-flop sincronizado por flanco de subida Flip-flops Summary The J-K flip-flop is more versatile than the flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge). J Inputs K Outputs Comments No change RESET SET 1 1 Toggle 0 0 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved

10 Funcionamiento J K Notice that the outputs change on the leading edge of the clock. Set Toggle Set Latch J K Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Funcionamiento del flip-flop J-K sincronizado por flanco de bajada

11 Summary Entradas asíncronas Synchronous inputs are transferred in the triggering edge of the clock (for example the or J-K inputs). Most flipflops have other inputs that are asynchronous, meaning they affect the output independent of the clock. Two such inputs are normally labeled preset (PRE) and clear (CLR). These inputs are usually active LOW. A J-K flip flop with active LOW preset and CLR is shown. PRE J K CLR Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved PRE Funcionamiento J K J CLR Set Toggle Set Reset Toggle Latch K PRE CLR Set Reset Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved

12 Resumen de los flips-flops

13 Flip-flop Characteristics Summary The propagation delay time is the time required for an input to cause a change in the output. It is measured from the 50% levels. Figure Propagation delays, clock to output. Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Retrasos de propagación de las entradas asíncronas Figure Propagation delays, preset input to output and clear input to output.

14 Flip-flop Characteristics Summary Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop. Setup time is the minimum time for the data to be present before the clock. Set-up time, t s Hold time is the minimum time for the data to remain after the clock. Hold time, t H Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Set-up time Figure Set-up time (t s ). The logic level must be present on the input for a time equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry.

15 Hold time Figure Hold time (t h ). The logic level must remain on the input for a time equal to or greater than t h after the triggering edge of the clock pulse for reliable data entry.

16 Summary Flip-flop Applications Principal flip-flop applications are for temporary data storage, as frequency dividers, and in counters (which are covered in detail in Chapter 10). C C R Output lines 0 1 R Typically, for data storage applications, a group of flip-flops are connected to parallel data lines and clocked together. ata is stored until the next clock pulse. Parallel data input lines Clock C R C 2 3 Clear R Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Figure Example of flip-flops used in a basic register for parallel data storage.

17 Flip-flop Applications Summary For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to continue to divide by two. One flip-flop will divide f in by 2, two flip-flops will divide f in by 4 (and so on). A side benefit of frequency division is that the output has an exact 50% duty cycle. Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ All Rights Reserved Figure The J-K flip-flop as a divide-by-2 device. is one-half the frequency of.

18 Figure Example of two J-K flip-flops used to divide the clock frequency by 4. A is one-half and B is one-fourth the frequency of.

19 Aplicación: generar una cuenta Figure Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown. Ejemplo: determinar la cuenta generada

20 Selected Key Terms Latch Bistable Clock flip-flop J-K flip-flop A bistable digital circuit used for storing a bit. Having two stable states. Latches and flip-flops are bistable multivibrators. A triggering input of a flip-flop. A type of bistable multivibrator in which the output assumes the state of the input on the triggering edge of a clock pulse. A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes. Selected Key Terms Propagation delay time Set-up time Hold time Timer Registered The interval of time required after an input signal has been applied for the resulting output signal to change. The time interval required for the input levels to be on a digital circuit. The time interval required for the input levels to remain steady to a flip-flop after the triggering edge in order to reliably activate the device. A circuit that can be used as a one-shot or as an oscillator. A CPL macrocell output configuration where the output comes from a flip-flop.

21 1. The output of a latch will not change if a. the output is LOW b. Enable is not active c. is LOW d. all of the above Pearson Pearson Education Education 2. The flip-flop shown will a. set on the next clock pulse b. reset on the next clock pulse c. latch on the next clock pulse d. toggle on the next clock pulse

22 3. For the J-K flip-flop shown, the number of inputs that are asynchronous is a. 1 b. 2 c. 3 d. 4 J K PRE CLR Pearson Pearson Education Education 4. Assume the output is initially HIGH on a leading edge triggered J-K flip flop. For the inputs shown, the output will go from HIGH to LOW on which clock pulse? a. 1 b. 2 c. 3 d. 4 J K

23 5. The time interval illustrated is called a. t PHL 50% point on triggering edge b. t PLH c. set-up time d. hold time? 50% point on LOW-to- HIGH transition of Pearson Pearson Education Education 6. The time interval illustrated is called a. t PHL b. t PLH c. set-up time d. hold time?

24 7. The application illustrated is a a. astable multivibrator HIGH HIGH b. data storage device c. frequency multiplier d. frequency divider f in J A K J B K f out Pearson Pearson Education Education 8. The application illustrated is a a. astable multivibrator b. data storage device c. frequency multiplier d. frequency divider Parallel data input lines C C C R R R Output lines Clock C 3 Clear R

25 9. A retriggerable one-shot with an active HIGH output has a pulse width of 20 ms and is triggered from a 60 Hz line. The output will be a a. series of 16.7 ms pulses b. series of 20 ms pulses c. constant LOW d. constant HIGH Pearson Pearson Education Education Answers: 1. b 6. d 2. d 7. d 3. b 8. b 4. c 9. d 5. b 10. a

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