Asynchronous counters, except for the first block, work independently from a system clock.


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1 Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flipflops, they can be asynchronous or synchronous and they can count in a forward or backward direction. Asynchronous counters Asynchronous counters, except for the first block, work independently from a system clock. Ripple counter The ripple counter is the simplest of all the counters. It belongs to the family of asynchronous counters because the blocks that make it up do not work with the clock at the same time (only the first block receives the clock). The reason why this counter is called a ripple counter is due to the fact the circuit begins counting from the lowest significant bit (LSB) and proceeds to the most significant bit (MSB) by rippling the count through the circuit. The circuit uses any nbit configuration and it counts up to n . A B C D UA UA UA UA 7LS07A 7LS07A 7LS07A 7LS07A OFFTIME =.5uS ONTIME =.5uS DELAY = 0ns STARTAL = OPPAL = 0 OFFTIME = s ONTIME =.us DELAY = us STARTAL = OPPAL = 0 bit ripple counter Ripple counters can be easily implemented with flipflops which can be configured to work like T flipflops. The above circuit is a bit ripple counter that counts from 0000 to. Before the first clock pulse comes (), the circuit is cleared () and its internal count is set to Each flipflop has its and inputs tied together to provide the functionality of the T flipflop (toggle with = and =). This circuit uses activelow logic (the 707A IC has a bubble in front of the symbol).
2 The disadvantage of this counter is that its simple design does not take into account its internal propagation delay. Higher bits depend on lower bits so this counter is inherently slow. The waveforms for this circuit are the followings: : : UA: UA: UA: UA: 0s us us 6us 8us 0us us us 6us 8us Time Waveforms for the bit ripple counter Initially, as shown above, the counter s contents are undefined so they are cleared and set to 0000 by. After that, a train of clock pulses increments the count by on every negative edge of the clock. The bits propagate and toggle. When the counter reaches, it overflows to 0000.
3 Synchronous counters Synchronous counters are directly dependently on a system clock. Binary counter (up) The binary counter is a modified version of the ripple counter. It belongs to the family of synchronous counters because the blocks that make it up work with the clock at the same time (all of them receive the clock). The reason why this counter is called a binary counter is due to the fact the circuit counts from 0 to n  (as opposed to the decimal counter which counts from 0 to 9). A B C D UA UA U5A 7LS08 UA U6A 7LS08 UA 7LS07A 7LS07A 7LS07A 7LS07A OFFTIME =.5uS ONTIME =.5uS DELAY = 0ns STARTAL = OPPAL = 0 OFFTIME = s ONTIME =.us DELAY = us STARTAL = OPPAL = 0 bit binary counter (up) Binary counters can be easily implemented with flipflops which can be configured to work like T flipflops. The above circuit is a bit binary counter that counts from 0000 to. Before the first clock pulse comes (), the circuit is cleared () and its internal count is set to Each flipflop has its and inputs tied together to provide the functionality of the T flipflop (toggle with = and =). This circuit uses activelow logic (the 707A IC has a bubble in front of the symbol). This binary counter is an improvement over the ripple counter. However, expanding to a higher number of bits requires additional AND gates. For a bit binary counter,  input AND gates are necessary. Expanding the counter to a 5bit counter would require additional input AND gate. This is to say that an nbit counter will require n flipflops and n input AND gates.
4 The waveforms for this circuit are as follows: : : UA: UA: U5A:B U5A:A 0s us us 6us 8us 0us us us 6us 8us Time Waveforms for the bit binary counter (up) Initially, as shown above, the counter s contents are undefined so they are cleared and set to 0000 by. After that, a train of clock pulses increments the count by on every negative edge of the clock. When the counter reaches, it overflows to PSpice simulates and warns about possible race conditions at all odd microseconds (starting from ). This is due to the fact the AND gates add propagation delay to the upper MSBs. The clock might arrive before the AND gates generate a bit and this might create a wrong counting sequence.
5 Binary counter (down) This counter is roughly equivalent to the previous. The only difference is that instead of counting up, it counts down ( n  to 0). A B C D UA UA U5A 7LS08 UA U6A 7LS08 UA 7LS07A 7LS07A 7LS07A 7LS07A OFFTIME =.5uS ONTIME =.5uS DELAY = 0ns STARTAL = OPPAL = 0 OFFTIME = s ONTIME =.us DELAY = us STARTAL = OPPAL = 0 bit binary counter (down) The only difference between the up and down versions of the binary counter is that one of the inputs to the AND gates is now and not like in the previous circuit. The count is still taken from the outputs. 5
6 The waveforms for this circuit are the followings: : : UA: UA: UA: UA: 0s 5us 0us 5us 0us Time Waveforms for the bit binary counter (down) Initially, as shown above, the counter s contents are undefined so they are cleared and set to 0000 by. After that, a train of clock pulses decrements the count by on every negative edge of the clock. When the counter reaches 0000, it overflows to. PSpice simulates and warns about possible race conditions at all even microseconds (starting from ). This is due to the fact the AND gates add propagation delay to the upper MSBs. The clock might arrive before the AND gates generate a bit and this might create a wrong counting sequence. 6
7 Binary counter (up/down) The up and down versions of the binary counter can be combined into a single circuit and form a binary up/down counter. This counter can count from 0 to n  and from n  to 0. A B C OFFTIME = 6uS UD0 ONTIME = 6uS DELAY = 50ns STARTAL = 0 OPPAL = OFFTIME =.5uS ONTIME =.5uS DELAY = 0ns U5A 7LS0 UA 7LS07A U6A 7LS08 U7A 7LS08 U8A 7LS U9A 7LS08 UA 7LS07A U0A 7LS08 UA 7LS UA 7LS08 UA 7LS07A UA 7LS08 UA 7LS D UA 7LS07A STARTAL = OPPAL = 0 OFFTIME = s ONTIME =.us DELAY = us STARTAL = OPPAL = 0 bit binary counter (up/down) The up counter is enabled when signal UD0=. The upper part of the circuit is active and the bottom part is turned off. The down counter is enabled when UD0=0. The lower part of the circuit is active and the top part is turned off. In order to provide the correct logic and enable/disable a specific part of the circuit to count up or down, this circuit needs additional gates: NOT, AND and OR gates. This circuit can be expanded to any nbit configuration by adding extra gates ( OR and ANDs). 7
8 The waveforms for this circuit are the followings: UD0: : : UA: UA:B UA: 0s us 8us us 6us 0us us 8us us Time Waveforms for the bit binary counter (up/down) As shown above, the counter starts by counting up (UD0=). Initially, the counter s contents are undefined so they are cleared and set to 0000 by. After that, a train of clock pulses increments the count by on every negative edge of the clock. After the counter reaches, the counter starts to count down (UD0=0). The train of clock pulses decrements the count by on every negative edge of the clock until the contents of the counter are
9 Decimal counter (up) The decimal counter is a modified version of the binary counter. It belongs to the family of synchronous counters because the blocks that make it up work with the clock at the same time (all of them receive the clock). The reason why this counter is called a decimal counter is due to the fact the circuit counts from 0 to 9 (as opposed to the binary counter which counts from 0 to n ). A B C U8A 7LS08 D UA U5A 7LS08 UA U6A 7LS08 UA U7A 7LS08 UA 7LS07A 7LS07A 7LS07A 7LS07A OFFTIME =.5uS ONTIME =.5uS DELAY = 0ns STARTAL = OPPAL = 0 OFFTIME = s ONTIME =.us DELAY = us STARTAL = OPPAL = 0 bit decimal counter (up) Decimal counters can be easily implemented with flipflops which can be configured to work like T flipflops. The above circuit is a bit decimal counter that counts from 0000 to 00. Before the first clock pulse comes (), the circuit is cleared () and its internal count is set to Each flipflop has its and inputs tied together to provide the functionality of the T flipflop (toggle with = and =). This circuit uses activelow logic (the 707A IC has a bubble in front of the symbol). This decimal counter is a variation of the binary counter. For the same size of bits, if compared to the binary counter, the decimal counter needs additional input AND gates and a slightly different routing ( feedback lines to the additional gates). For a bit binary counter, input AND gates are necessary. 9
10 The waveforms for this circuit are the followings: : : U8A:B U7A:B U6A:B UA: 0s us us 6us 8us 0us us Time Waveforms for the bit decimal counter Initially, as shown above, the counter s contents are undefined so they are cleared and set to 0000 by. After that, a train of clock pulses increments the count by on every negative edge of the clock. When the counter reaches 00, it overflows to PSpice simulates but, unlike for previous counters, no longer warns about possible race conditions because all flipflops are associated to the same amount of delay produced by the AND gates (except for UA which is constantly held at and therefore immune to race conditions). 0
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