# 路 論 Chapter 15 System-Level Physical Design

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1 Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007

2 Outline Clocked Flip-flops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations

3 Clocked Flip-flops Synchronous design employs clocking signals to coordinate the movement of data through the system In Figure 15.2, the data bit D is loaded into the DFF only on a rising clock edge Q t + t ff ) = D( ) (15.1) ( 0 t0 Where t o is the rise edge, and t ff is the time delay when the output has this value In high speed design, the limiting circuit factor is the DFF delay time t ff that is determined by the electronics and the load» Decreasing t ff allows for a higher frequency clock» The tradeoff of speed and power Figure 15.1 Ideal clocking signal Figure 15.2 Timing in a DFF

4 Classical State Machines (1/2) Two models for state machines that use single-clock timing are shown in Figure 15.3» Moore machine and Mealy machine» Huffman model (Figure 15.4): contains both the Moore and Mealy models (a) Moore machine (b) Mealy machine Figure 15.3 Moore and mealy state machines Figure 15.4 Huffman model of a state machine

5 Classical State Machines (2/2) FPGA design are also heavily based on classical state machine theory» For examples, in combinational logic, Individual gates, PLAs, Programming Logic Device (PLD), and groups of multiplexors» Programming is achieved with EPROMs, fuses, SRAM arrays, and some contain lookup tables (LUT, e.g. FPGA) to aid in the design In Figure 15.5 m r r T > t + t + t ff d su (15.2) (15.3) (The AND-plane of the PLA can be programmed to produce minterms m r ) (The clock T must be large enough to allow completion) Where, t ff is the delay time form input to output of the flip-flop t d is the logic delay time through the PLA t su is the setup time of the flip-flip Figure 15.5 Huffman state machine using PLA logic

6 Outline Clocked Flip-flops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations

7 Clocked Logic Cascades Ideal waveforms for the complimentary signal φ φ = 0 (15.4) (Figure 15.6) V max = V DD V Tn (15.5) (Figure 15.7) (a) FETs (b) Transmission gate Figure 15.7 Clock-controlled transistors Figure 15.6 Complementary clocks Figure 15.8 A clocked cascade

8 Timing Circles and Clock Skew Timing circles: are simple constructs that can be useful for visualizing data transfer» In Figure 15.9, this defines what is known as a 50% duty cycle Clock skew: the timing of a clock is out of phase with the system reference Figure Clock generation circuit Figure Clock skew Figure 15.9 Timing circle for a single-clock, dual-phase cascade Figure Timing circle with clock skew

9 Circuit Effects and Clock Frequency (1/2) The logic-level description of the clocked cascade masks the circuit characteristics that determine the ultimate speed T 2 min = t FET + t NOT (15.7) f 1 = T min = max 1 2 t h (15.12) T 2 f f I max max leak T 2 min 1 = T = t r + t min 1 = T min = C max = in t h, FET HL, NOT 1 = 2( t r + t, FET 1 = 2( t r + t dv dt in, FET HL, NOT CL ) (15.8) ) (15.11) (15.12) (15.9) (15.10) V M V = DD V Tp 1+ W κ n ' β n L n = β p W κ p ' L : β n κ n ' = β κ ' p p p + β β n p β n V β p Tn (15.14) (15.15) (15.13) Figure Shift register circuit (a) Circuit (b) Voltage decay Figure Charge leakage in the shift register

10 Circuit Effects and Clock Frequency (2/2) Figure Clocking waveforms with finite rise and fall times Figure Static shift register design

11 Dual Non-overlapping Clocks In this technique, two distinct non-overlapping clocks 1 and 2 are used such that (Fig and 15.18) φ t) φ ( t) 0 (15.17) 1 ( 2 = Finite-state machines that are based on dualclock schemes can provide powerful interactive capabilities (Fig ) Figure Timing circuit for a 2-clock network Figure Dual non-overlapping clocks Figure A dual-clock finite-state machine design

12 Other Multiple-clock Schemes It is possible to create different mutlipleclock schemes to control clocked logic cascades and state machine» For example, a triple, non-overlapping clock set However, in modern high-speed VLSI, complicated clocking schemes introduce too many problems» Solution: speed gains are accomplished by improved circuit design, processing, and architectural modifications» The most popular approach is to use a single-clock, dual-phase system Figure Triple, non-overlapping clock signals Figure Timing circle for a 3-clock non-overlapping network

13 Dynamic Logic Cascades (1/2) Dynamic logic circuits achieve synchronized data flow by controlling the internal operational states of the logic gate circuits» Typical domino logic state: In section 9.5 of Chapter 9» P: per-charge phase» E: Evaluation phase In Figure 15.23, Figure Operation of a domino logic state Figure A dynamic logic cascade

14 Dynamic Logic Cascades (2/2) In Figure 15.24, the data transfer into and out of a dynamic logic cascade is sequenced with the clock» The number of stages that can be included in the chain is determined by the delay for the case where every stage switches» However, this introduces charge leakage problem» Solution: charge keeper circuits True Single-Phase Clock (TSPC): use only a single clock throughout» Two TSPC latches are shown in Figure Figure Timing sequence in the domino cascade (a) n-block (b) p-block Figure True single-phase clock latches

15 Outline Clocked Flip-flops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations

16 Basic Concept of Pipelining Pipelining is a tech. that is used to increase the throughput of a sequential set of distinct data inputs through a synchronous logic cascade T > t + t + t + t ff d su s (15.18) Figure Basic pipelined stage for timing analysis t hold < PW (15.19) (PW: pulse width of the clock) f < t ff + t d 1 + t su + t s (15.20) Where, t ff : flip-flop delay time t d : logic delay time t su : setup time of the flip-flip t hold : hold time of the flip-flip Figure Waveform quantities for timing analysis

17 Pipelining (1/2) Pipelined systems are designed to increase the overall throughput of a set of sequential input states by dividing the cascade into small visualization of the problem (Figure 15.28) Once a circuit completes a calculation and passes the result on to the next stage, it remain idle for the rest of the clock cycle (Figure 15.29) Figure Logic chains in a clocked system Figure Circuit activity in a logic cascade

18 Pipelining (2/2) Since the delay through a logic gate varies its complexity and parasitics, the logic propagation rate will not be uniform Figure A 4-stage pipeline Figure Progression times in the logic cascade In Figure 15.31, dividing the long logic into small groups, add registers between the sections, and use a faster clock, then most of the circuits will be active at any given time 4 T + ( N 1) T = ( N + 3) T T pipe pipe i > t ff + t su + td, i + ts, i+ 1 T pipe = max{ T 1,..., T m } pipe (15.21) (15.22) (15.23) Figure Pipeline with positive edge and negative edge-triggering

19 Outline Clocked Flip-flops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations

20 Clock Distribution When frequencies f reach the 1GHz (10 9 Hz) level corresponding to a clock period of 1 T = = 1 f ns However, distribution of the clocking signal to various points of the chip is complicated because the intrinsic RC time delay increases as the square of the line length l according to τ = 2 Bl (15.24) (15.25) Figure A 4-stage pipeline t t = B( l b la = B( l c lb ) ) (15.26) (15.27) Problems: clock skew and signal distortion will be very difficult to deal with in large chips Figure A 4-stage pipeline

21 Clock Stabilization and Generation (1/2) Figure A basic clock stabilization network Figure Phase-locked loop (PLL) stabilization circuit

22 Clock Stabilization and Generation (2/2) Figure Inverter-based clock generation circuit C = C line + CG (15.28) Figure Generating complementary clocks using a latch Figure Skew minimization circuit Figure Circuit for producing non-overlapping clocks

23 Clock Routing and Driver Trees (a) Clocking points (b) First grouping (c) Interior routing Figure Simplified view of the clock routing problem (a) First (b) Second (c) Third (d) Routing Figure Partitioning steps for defining clocking groups

24 Driver Tree (1/2) Figure Geometrical analysis of the letter H (a) Driver tree (b) Application to H-tree Figure Driver tree arrangement Figure Macro-level H-type distribution tree Figure Driver tree design with interconnect parasitics

25 Driver Tree (2/2) (a) Driver tree (b) Chip distribution Figure Distribution scheme with equivalent driver segments Figure Single driver tree with multiple outputs Figure Electrical circuit for a non-symmetrical distribution Figure Asynchronous system clocking Figure Operation of a self-timed element

26 Outline Clocked Flip-flops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations

27 Bit Slice Design (1/2) For example, an ALU circuit design (Fig ) C = C( A, B; control) (15.30) Bit slice design is based on the fact that logic deals with data at the bit-level Figure An n-bit ALU Figure Block description

28 Bit Slice Design (2/2) With the bit slice philosophy, an n-bit ALU is created by paralleling n identical slices as shown in Figure 15.55» The repetition will also appear at the logic, circuit, and silicon levels» Advantage: library and instance building for large system design For example, in Verilog Figure An ALU bit slice reg A, B, C; (1-bit data-type) reg[ 31,0] A, B, C; (32-bit data-type) Figure ALU design with bit slices

29 Cache Memory Cache memory is designed to be place in between the CPU and the main memory to speed up the system operation» SRAM memory structure» Instruction-cache (I-cache) : is used to hold instructions that are fetched from the M.M. where the program to run freely» Data-cache (D-cache): is used to hold the results of computations Figure shows a simple block diagram for a dual-issue superscalar design using I- cache and D-cache (Computer Architecture) (a) Basic system (b) Cache modification Figure Adding cache memory Figure Block diagram of a dualissue superscalar machine

30 Systolic Systems and Parallel Processing In a systolic system, the movement of the data is controlled by a clock, moving one phase on each cycle In parallel processing, a PE (processor element) can be as simple as an AND gate, or as a complex as a general-purpose microprocessor (Fig )» Individual process elements communicate via switching arrays, which are controlled by either local or global signals» The strongest aspects of VLSI: Wafer scale integration, WSI Figure Regular patterning in a parallel processing network

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