路 論 Chapter 15 SystemLevel Physical Design


 Benedict Crawford
 3 years ago
 Views:
Transcription
1 Introduction to VLSI Circuits and Systems 路 論 Chapter 15 SystemLevel Physical Design Dept. of Electronic Engineering National ChinYi University of Technology Fall 2007
2 Outline Clocked Flipflops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations
3 Clocked Flipflops Synchronous design employs clocking signals to coordinate the movement of data through the system In Figure 15.2, the data bit D is loaded into the DFF only on a rising clock edge Q t + t ff ) = D( ) (15.1) ( 0 t0 Where t o is the rise edge, and t ff is the time delay when the output has this value In high speed design, the limiting circuit factor is the DFF delay time t ff that is determined by the electronics and the load» Decreasing t ff allows for a higher frequency clock» The tradeoff of speed and power Figure 15.1 Ideal clocking signal Figure 15.2 Timing in a DFF
4 Classical State Machines (1/2) Two models for state machines that use singleclock timing are shown in Figure 15.3» Moore machine and Mealy machine» Huffman model (Figure 15.4): contains both the Moore and Mealy models (a) Moore machine (b) Mealy machine Figure 15.3 Moore and mealy state machines Figure 15.4 Huffman model of a state machine
5 Classical State Machines (2/2) FPGA design are also heavily based on classical state machine theory» For examples, in combinational logic, Individual gates, PLAs, Programming Logic Device (PLD), and groups of multiplexors» Programming is achieved with EPROMs, fuses, SRAM arrays, and some contain lookup tables (LUT, e.g. FPGA) to aid in the design In Figure 15.5 m r r T > t + t + t ff d su (15.2) (15.3) (The ANDplane of the PLA can be programmed to produce minterms m r ) (The clock T must be large enough to allow completion) Where, t ff is the delay time form input to output of the flipflop t d is the logic delay time through the PLA t su is the setup time of the flipflip Figure 15.5 Huffman state machine using PLA logic
6 Outline Clocked Flipflops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations
7 Clocked Logic Cascades Ideal waveforms for the complimentary signal φ φ = 0 (15.4) (Figure 15.6) V max = V DD V Tn (15.5) (Figure 15.7) (a) FETs (b) Transmission gate Figure 15.7 Clockcontrolled transistors Figure 15.6 Complementary clocks Figure 15.8 A clocked cascade
8 Timing Circles and Clock Skew Timing circles: are simple constructs that can be useful for visualizing data transfer» In Figure 15.9, this defines what is known as a 50% duty cycle Clock skew: the timing of a clock is out of phase with the system reference Figure Clock generation circuit Figure Clock skew Figure 15.9 Timing circle for a singleclock, dualphase cascade Figure Timing circle with clock skew
9 Circuit Effects and Clock Frequency (1/2) The logiclevel description of the clocked cascade masks the circuit characteristics that determine the ultimate speed T 2 min = t FET + t NOT (15.7) f 1 = T min = max 1 2 t h (15.12) T 2 f f I max max leak T 2 min 1 = T = t r + t min 1 = T min = C max = in t h, FET HL, NOT 1 = 2( t r + t, FET 1 = 2( t r + t dv dt in, FET HL, NOT CL ) (15.8) ) (15.11) (15.12) (15.9) (15.10) V M V = DD V Tp 1+ W κ n ' β n L n = β p W κ p ' L : β n κ n ' = β κ ' p p p + β β n p β n V β p Tn (15.14) (15.15) (15.13) Figure Shift register circuit (a) Circuit (b) Voltage decay Figure Charge leakage in the shift register
10 Circuit Effects and Clock Frequency (2/2) Figure Clocking waveforms with finite rise and fall times Figure Static shift register design
11 Dual Nonoverlapping Clocks In this technique, two distinct nonoverlapping clocks 1 and 2 are used such that (Fig and 15.18) φ t) φ ( t) 0 (15.17) 1 ( 2 = Finitestate machines that are based on dualclock schemes can provide powerful interactive capabilities (Fig ) Figure Timing circuit for a 2clock network Figure Dual nonoverlapping clocks Figure A dualclock finitestate machine design
12 Other Multipleclock Schemes It is possible to create different mutlipleclock schemes to control clocked logic cascades and state machine» For example, a triple, nonoverlapping clock set However, in modern highspeed VLSI, complicated clocking schemes introduce too many problems» Solution: speed gains are accomplished by improved circuit design, processing, and architectural modifications» The most popular approach is to use a singleclock, dualphase system Figure Triple, nonoverlapping clock signals Figure Timing circle for a 3clock nonoverlapping network
13 Dynamic Logic Cascades (1/2) Dynamic logic circuits achieve synchronized data flow by controlling the internal operational states of the logic gate circuits» Typical domino logic state: In section 9.5 of Chapter 9» P: percharge phase» E: Evaluation phase In Figure 15.23, Figure Operation of a domino logic state Figure A dynamic logic cascade
14 Dynamic Logic Cascades (2/2) In Figure 15.24, the data transfer into and out of a dynamic logic cascade is sequenced with the clock» The number of stages that can be included in the chain is determined by the delay for the case where every stage switches» However, this introduces charge leakage problem» Solution: charge keeper circuits True SinglePhase Clock (TSPC): use only a single clock throughout» Two TSPC latches are shown in Figure Figure Timing sequence in the domino cascade (a) nblock (b) pblock Figure True singlephase clock latches
15 Outline Clocked Flipflops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations
16 Basic Concept of Pipelining Pipelining is a tech. that is used to increase the throughput of a sequential set of distinct data inputs through a synchronous logic cascade T > t + t + t + t ff d su s (15.18) Figure Basic pipelined stage for timing analysis t hold < PW (15.19) (PW: pulse width of the clock) f < t ff + t d 1 + t su + t s (15.20) Where, t ff : flipflop delay time t d : logic delay time t su : setup time of the flipflip t hold : hold time of the flipflip Figure Waveform quantities for timing analysis
17 Pipelining (1/2) Pipelined systems are designed to increase the overall throughput of a set of sequential input states by dividing the cascade into small visualization of the problem (Figure 15.28) Once a circuit completes a calculation and passes the result on to the next stage, it remain idle for the rest of the clock cycle (Figure 15.29) Figure Logic chains in a clocked system Figure Circuit activity in a logic cascade
18 Pipelining (2/2) Since the delay through a logic gate varies its complexity and parasitics, the logic propagation rate will not be uniform Figure A 4stage pipeline Figure Progression times in the logic cascade In Figure 15.31, dividing the long logic into small groups, add registers between the sections, and use a faster clock, then most of the circuits will be active at any given time 4 T + ( N 1) T = ( N + 3) T T pipe pipe i > t ff + t su + td, i + ts, i+ 1 T pipe = max{ T 1,..., T m } pipe (15.21) (15.22) (15.23) Figure Pipeline with positive edge and negative edgetriggering
19 Outline Clocked Flipflops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations
20 Clock Distribution When frequencies f reach the 1GHz (10 9 Hz) level corresponding to a clock period of 1 T = = 1 f ns However, distribution of the clocking signal to various points of the chip is complicated because the intrinsic RC time delay increases as the square of the line length l according to τ = 2 Bl (15.24) (15.25) Figure A 4stage pipeline t t = B( l b la = B( l c lb ) ) (15.26) (15.27) Problems: clock skew and signal distortion will be very difficult to deal with in large chips Figure A 4stage pipeline
21 Clock Stabilization and Generation (1/2) Figure A basic clock stabilization network Figure Phaselocked loop (PLL) stabilization circuit
22 Clock Stabilization and Generation (2/2) Figure Inverterbased clock generation circuit C = C line + CG (15.28) Figure Generating complementary clocks using a latch Figure Skew minimization circuit Figure Circuit for producing nonoverlapping clocks
23 Clock Routing and Driver Trees (a) Clocking points (b) First grouping (c) Interior routing Figure Simplified view of the clock routing problem (a) First (b) Second (c) Third (d) Routing Figure Partitioning steps for defining clocking groups
24 Driver Tree (1/2) Figure Geometrical analysis of the letter H (a) Driver tree (b) Application to Htree Figure Driver tree arrangement Figure Macrolevel Htype distribution tree Figure Driver tree design with interconnect parasitics
25 Driver Tree (2/2) (a) Driver tree (b) Chip distribution Figure Distribution scheme with equivalent driver segments Figure Single driver tree with multiple outputs Figure Electrical circuit for a nonsymmetrical distribution Figure Asynchronous system clocking Figure Operation of a selftimed element
26 Outline Clocked Flipflops CMOS Clocking Styles Pipelined Systems Clock Generation and Distribution System Design Considerations
27 Bit Slice Design (1/2) For example, an ALU circuit design (Fig ) C = C( A, B; control) (15.30) Bit slice design is based on the fact that logic deals with data at the bitlevel Figure An nbit ALU Figure Block description
28 Bit Slice Design (2/2) With the bit slice philosophy, an nbit ALU is created by paralleling n identical slices as shown in Figure 15.55» The repetition will also appear at the logic, circuit, and silicon levels» Advantage: library and instance building for large system design For example, in Verilog Figure An ALU bit slice reg A, B, C; (1bit datatype) reg[ 31,0] A, B, C; (32bit datatype) Figure ALU design with bit slices
29 Cache Memory Cache memory is designed to be place in between the CPU and the main memory to speed up the system operation» SRAM memory structure» Instructioncache (Icache) : is used to hold instructions that are fetched from the M.M. where the program to run freely» Datacache (Dcache): is used to hold the results of computations Figure shows a simple block diagram for a dualissue superscalar design using I cache and Dcache (Computer Architecture) (a) Basic system (b) Cache modification Figure Adding cache memory Figure Block diagram of a dualissue superscalar machine
30 Systolic Systems and Parallel Processing In a systolic system, the movement of the data is controlled by a clock, moving one phase on each cycle In parallel processing, a PE (processor element) can be as simple as an AND gate, or as a complex as a generalpurpose microprocessor (Fig )» Individual process elements communicate via switching arrays, which are controlled by either local or global signals» The strongest aspects of VLSI: Wafer scale integration, WSI Figure Regular patterning in a parallel processing network
Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology
Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Twophase clocking. Testing of combinational (Chapter 4) and sequential (Chapter
More informationIntroduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems
Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH
More informationLecture 7: Clocking of VLSI Systems
Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 TwoPhase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10  Clocking Note: The analysis
More informationSequential Circuit Design
Sequential Circuit Design LanDa Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines
More informationPower Reduction Techniques in the SoC Clock Network. Clock Power
Power Reduction Techniques in the SoC Network Low Power Design for SoCs ASIC Tutorial SoC.1 Power Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a
More informationTiming Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
More informationClocking. Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 Clocks 1
ing Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884  Spring 2005 2/18/05
More informationLecture 11: Sequential Circuit Design
Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Minelay Clock Skew Time Borrowing TwoPhase Clocking 2 Sequencing Combinational logic output depends on current
More informationLecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Minelay q Clock Skew q Time Borrowing
More informationPowerPC Microprocessor Clock Modes
nc. Freescale Semiconductor AN1269 (Freescale Order Number) 1/96 Application Note PowerPC Microprocessor Clock Modes The PowerPC microprocessors offer customers numerous clocking options. An internal phaselock
More informationModeling Sequential Elements with Verilog. Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 41 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit  FSM A Sequential circuit contains: Storage
More informationTRUE SINGLE PHASE CLOCKING BASED FLIPFLOP DESIGN
TRUE SINGLE PHASE CLOCKING BASED FLIPFLOP DESIGN USING DIFFERENT FOUNDRIES Priyanka Sharma 1 and Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department
More informationChapter 7 Memory and Programmable Logic
NCNU_2013_DD_7_1 Chapter 7 Memory and Programmable Logic 71I 7.1 Introduction ti 7.2 Random Access Memory 7.3 Memory Decoding 7.5 Read Only Memory 7.6 Programmable Logic Array 77P 7.7 Programmable Array
More informationSequential Circuits. Combinational Circuits Outputs depend on the current inputs
Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating
More informationNAME AND SURNAME. TIME: 1 hour 30 minutes 1/6
E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 20052006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June
More informationTwoPhase Clocking Scheme for LowPower and High Speed VLSI
International Journal of Advances in Engineering Science and Technology 225 www.sestindia.org/volumeijaest/ and www.ijaestonline.com ISSN: 23191120 TwoPhase Clocking Scheme for LowPower and High Speed
More informationAgenda. Michele Taliercio, Il circuito Integrato, Novembre 2001
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
More informationS. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India
Power reduction on clocktree using Energy recovery and clock gating technique S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Abstract Power consumption of
More informationModule 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1
Module 2 Embedded Processors and Memory Version 2 EE IIT, Kharagpur 1 Lesson 5 MemoryI Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would PreRequisite
More informationLatch Timing Parameters. Flipflop Timing Parameters. Typical Clock System. Clocking Overhead
Clock  key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationComputer Architecture
Computer Architecture Random Access Memory Technologies 2015. április 2. Budapest Gábor Horváth associate professor BUTE Dept. Of Networked Systems and Services ghorvath@hit.bme.hu 2 Storing data Possible
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationEE411: Introduction to VLSI Design Course Syllabus
: Introduction to Course Syllabus Dr. Mohammad H. Awedh Spring 2008 Course Overview This is an introductory course which covers basic theories and techniques of digital VLSI design in CMOS technology.
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS
More informationLecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Minelay
More informationClock Distribution in RNSbased VLSI Systems
Clock Distribution in RNSbased VLSI Systems DANIEL GONZÁLEZ 1, ANTONIO GARCÍA 1, GRAHAM A. JULLIEN 2, JAVIER RAMÍREZ 1, LUIS PARRILLA 1 AND ANTONIO LLORIS 1 1 Dpto. Electrónica y Tecnología de Computadores
More informationDATA SHEET. HEF40193B MSI 4bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
More informationDESIGN CHALLENGES OF TECHNOLOGY SCALING
DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE
More informationDigital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian Email: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief Email: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An nbit register
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationSequential 4bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationAlpha CPU and Clock Design Evolution
Alpha CPU and Clock Design Evolution This lecture uses two papers that discuss the evolution of the Alpha CPU and clocking strategy over three CPU generations Gronowski, Paul E., et.al., High Performance
More informationStaticNoiseMargin Analysis of Conventional 6T SRAM Cell at 45nm Technology
StaticNoiseMargin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FETMITS (Deemed university), Lakshmangarh, India B. P. Singh Department
More informationRAM & ROM Based Digital Design. ECE 152A Winter 2012
RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in
More informationLayout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
More informationComputer Systems Structure Main Memory Organization
Computer Systems Structure Main Memory Organization Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Storage/Memory
More informationArchitectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng
Architectural Level Power Consumption of Network Presenter: YUAN Zheng Why Architectural Low Power Design? Highspeed and large volume communication among different parts on a chip Problem: Power consumption
More informationCounters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flipflop values themselves, serves as the output. The output value increases by one on each clock cycle.
More informationDM74LS169A Synchronous 4Bit Up/Down Binary Counter
Synchronous 4Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry lookahead for cascading in highspeed counting applications. Synchronous operation
More informationReadonly memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards
Points ddressed in this Lecture Lecture 8: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Readonly memory Implementing logic with ROM Programmable logic
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationSequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
More informationChapter 9 Latches, FlipFlops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, FlipFlops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationWe r e going to play Final (exam) Jeopardy! "Answers:" "Questions:"  1 
. (0 pts) We re going to play Final (exam) Jeopardy! Associate the following answers with the appropriate question. (You are given the "answers": Pick the "question" that goes best with each "answer".)
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd Chapter 1 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved Analog Quantities Most natural quantities that we see
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationLow Power AMD Athlon 64 and AMD Opteron Processors
Low Power AMD Athlon 64 and AMD Opteron Processors Hot Chips 2004 Presenter: Marius Evers Block Diagram of AMD Athlon 64 and AMD Opteron Based on AMD s 8 th generation architecture AMD Athlon 64 and AMD
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationFault Modeling. Why model faults? Some real defects in VLSI and PCB Common fault models Stuckat faults. Transistor faults Summary
Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuckat faults Single stuckat faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuckat
More informationMcPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures
McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Sheng Li, Junh Ho Ahn, Richard Strong, Jay B. Brockman, Dean M Tullsen, Norman Jouppi MICRO 2009
More informationTIMINGDRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING
TIMINGDRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation
More informationCHAPTER 11 LATCHES AND FLIPFLOPS
CHAPTER 11 LATCHES AND FLIPFLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 SetReset Latch 11.3 Gated D Latch 11.4 EdgeTriggered D FlipFlop 11.5 SR FlipFlop
More informationCSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap 5, App. A& B) Number representations Boolean algebra OP and PO Logic
More informationCHAPTER 5 FINITE STATE MACHINE FOR LOOKUP ENGINE
CHAPTER 5 71 FINITE STATE MACHINE FOR LOOKUP ENGINE 5.1 INTRODUCTION Finite State Machines (FSMs) are important components of digital systems. Therefore, techniques for area efficiency and fast implementation
More informationIntroduction to Programmable Logic Devices. John Coughlan RAL Technology Department Detector & Electronics Division
Introduction to Programmable Logic Devices John Coughlan RAL Technology Department Detector & Electronics Division PPD Lectures Programmable Logic is Key Underlying Technology. FirstLevel and HighLevel
More informationAsynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton Dept. of Electrical and Computer Engineering University of British Columbia bradq@ece.ubc.ca
More information. MEDIUM SPEED OPERATION  8MHz (typ.) @ . MULTIPACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE
HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE. MEDIUM SPEED OPERATION  8MHz (typ.) @ CL = 50pF AND DDSS = 10. MULTIPACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RES
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit A Sequential circuit contains: Storage elements:
More informationModeling Latches and Flipflops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationLOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING
LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING A thesis work submitted to the faculty of San Francisco State University In partial fulfillment of the requirements for
More informationComputer organization
Computer organization Computer design an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine inputs
More informationECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8bit microprocessor data
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence
More informationThe components. E3: Digital electronics. Goals:
E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7segment display. 2 st. IC
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationMaster/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
More informationNOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual InLine Package.
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo6
More informationChapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
More informationLAB #4 Sequential Logic, Latches, FlipFlops, Shift Registers, and Counters
LAB #4 Sequential Logic, Latches, FlipFlops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flipflop 2. Use of actual flipflops to help you understand sequential
More informationInterconnection Networks
Advanced Computer Architecture (0630561) Lecture 15 Interconnection Networks Prof. Kasim M. AlAubidy Computer Eng. Dept. Interconnection Networks: Multiprocessors INs can be classified based on: 1. Mode
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationLab #5: Design Example: Keypad Scanner and Encoder  Part 1 (120 pts)
Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder  Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement
More informationOnchip clock error characterization for clock distribution system
Onchip clock error characterization for clock distribution system Chuan Shan, Dimitri Galayko, François Anceau Laboratoire d informatique de Paris 6 (LIP6) Université Pierre & Marie Curie (UPMC), Paris,
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate Kmaps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More informationHCC/HCF4032B HCC/HCF4038B
HCC/HCF4032B HCC/HCF4038B TRIPLE SERIAL ADDERS INERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS FULLY STATIC OPERATION...DC TO 10MHz (typ.) @ DD = 10 BUFFERED INPUTS AND OUTPUTS SINGLEPHASE
More informationDesign Example: Counters. Design Example: Counters. 3Bit Binary Counter. 3Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More information54191 DM54191 DM74191 Synchronous Up Down 4Bit Binary Counter with Mode Control
54191 DM54191 DM74191 Synchronous Up Down 4Bit Binary Counter with Mode Control General Description This circuit is a synchronous reversible up down counter The 191 is a 4bit binary counter Synchronous
More informationAC 20072485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)
AC 20072485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) Samuel Lakeou, University of the District of Columbia Samuel Lakeou received a BSEE (1974) and a MSEE (1976)
More informationChapter 2 Clocks and Resets
Chapter 2 Clocks and Resets 2.1 Introduction The cost of designing ASICs is increasing every year. In addition to the nonrecurring engineering (NRE) and mask costs, development costs are increasing due
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationTrue Single Phase Clocking FlipFlop Design using Multi Threshold CMOS Technique
True Single Phase Clocking FlipFlop Design using Multi Threshold CMOS Technique Priyanka Sharma ME (ECE) Student NITTTR Chandigarh Rajesh Mehra Associate Professor Department of ECE NITTTR Chandigarh
More informationComputer System: User s View. Computer System Components: High Level View. Input. Output. Computer. Computer System: Motherboard Level
System: User s View System Components: High Level View Input Output 1 System: Motherboard Level 2 Components: Interconnection I/O MEMORY 3 4 Organization Registers ALU CU 5 6 1 Input/Output I/O MEMORY
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. PuJen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits PuJen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationObsolete Product(s)  Obsolete Product(s)
SYNCHRONOUS PROGRAMMABLE 4BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOKAHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOWPOWER TTL COMPATIBILITY STANDARDIZED
More informationDM54161 DM74161 DM74163 Synchronous 4Bit Counters
DM54161 DM74161 DM74163 Synchronous 4Bit Counters General Description These synchronous presettable counters feature an internal carry lookahead for application in highspeed counting designs The 161
More informationEE552. Advanced Logic Design and Switching Theory. Metastability. Ashirwad Bahukhandi. (Ashirwad Bahukhandi) bahukhan@usc.edu
EE552 Advanced Logic Design and Switching Theory Metastability by Ashirwad Bahukhandi (Ashirwad Bahukhandi) bahukhan@usc.edu This is an overview of what metastability is, ways of interpreting it, the issues
More informationAll Programmable Logic. HansJoachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule
All Programmable Logic HansJoachim Gelke Institute of Embedded Systems Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries www.ines.zhaw.ch Research: Education:
More informationTopics. Flipflopbased sequential machines. Signals in flipflop system. Flipflop rules. Latchbased machines. Twosided latch constraint
Topics Flipflopbased sequential machines! Clocking disciplines. Flipflop rules! Primary inputs change after clock (φ) edge.! Primary inputs must stabilize before next clock edge.! Rules allow changes
More information54LS169 DM54LS169A DM74LS169A Synchronous 4Bit Up Down Binary Counter
54LS169 DM54LS169A DM74LS169A Synchronous 4Bit Up Down Binary Counter General Description This synchronous presettable counter features an internal carry lookahead for cascading in highspeed counting
More informationRegisters & Counters
Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multibit storage devices. Introduce counters by adding logic to registers implementing
More information