Design Example: Counters. Design Example: Counters. 3Bit Binary Counter. 3Bit Binary Counter. Other useful counters:


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1 Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary sequence. bit (up) binary counter:,,,. bit down binary counter: 7,,,,,,, Design Eample: ers Other useful counters: Decimal counter (e.g. BCD counter),,,,,,,, Modulok counter Modulo counter:,,,,,,,, MtoN counter to8 counter:,,,,7,8,,, Ripple counter Ring counter and ohnson counter Bit Binary er Bit Binary er (t) (t+) T current state net state flipflop inputs A B C A B C TA TB TC Flipflop input functions TA = BC TB = C TC = T A T B T C Figure. gives a bit binary counter. When =C, =B, =A, delete, set enable bit to be constant, it becomes this bit counter.
2 Binary er with FlipFlops E A Down Binary er E A (t) (t+) when E = and goes from to : A A A A A A A A A A Eercise: Verify that the circuit is a binary counter that counts down from to, and then back to again. A A A A A A A A Summary Binary er with Parallel Sequential circuit design eample Shift registers Basic counters Net time Binary counter with parallel Ripple counter ohnson counter Net Monday: Eam IV PLD, Chapter, 7., 7. Discussion on Wednesday s class control signals, modes: ( i =D i ) = (up) =, = No change =, = (change, or count, happens only at positive edge of the clock pulse.) Carry Out: if and only if the counter is in count mode with content. Read Figure. for the detailed implementation. D D
3 9 7 8 modulo Modulo7 er modulo7 (when to ) D D modulo To8 er D D to8 (when and what to ) Design Eample Eam IV 8bit counter with two ers D D D D 7 PLD Timing diagram for basic latch/flipflop Sequential circuit analysis Sequential circuit design Registers and counters
4 Ripple er Synchronous counter: the signal of all flipflops are from the common clock. Ripple counter: the of some flipflops are from other flipflops (and through logic gates). Ripple counter is asynchronous Binary ripple (up) counter (read Figure.) Binary ripple down counter Where the signal comes from? (By default, flipflop is positive edge triggered.) BCD Ripple er Verify the following circuit is a BCD Ripple counter triggered by negative edge. 8 BCD Ripple er Verify the following circuit is a BCD Ripple counter triggered by negative edge. Ring er Ring counter: a circular shift register (with k flipflops) that at any time, only one flipflop is set (having value ) and all others are cleared (with value ). It is used to generate k (periodic) timing signals. Eample: see Figure.7 for circuit. A D 8 C B
5 Ring er as er + Decoder ohnson er To generate (periodic) timing signals, we need a bit ring counter, or a bit counter and a decoder. bit count decoder D C B A ohnson counter: a kbit circular shift register with the complement of the last flipflop connected to the input of the first flipflop, and k decoding gates. It is used to generate k (periodic) timing signals. AND gates for decoding S S S D D D ohnson er S S S D D D states AND gate for output S S S T T T T T T AND gates for decoding S S S T = S S T = S S T = S S T = S S T = S S T = S S
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