Set-Reset (SR) Latch

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1 et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) + + Function eset et ? 0-? Indeterminate cross-coupled Nand gates active low inputs (only one can be active) + + Function ? 1-? Indeterminate et eset 1 1 C.. troud, ept. of C, Auburn Univ.

2 nabled et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs ( & cannot be active) + + Function 0 x x eset et ? 0-? Indeterminate cross-coupled Nand gates active low inputs ( & cannot be active) + + Function ? 1-? Indeterminate et eset x x C.. troud, ept. of C, Auburn Univ.

3 Transparent Latch Asynchronous Level sensitive cross-coupled Nor gates active high enable () + Function 0 x Transparent Mode Transparent Mode cross-coupled Nand gates active low enable () + Function 1 x Transparent Mode Transparent Mode C.. troud, ept. of C, Auburn Univ.

4 Flip-Flop ynchronous (also know as Master-lave FF) dge Triggered (data moves on clock transition) one latch transparent - the other in storage active low latch followed by active high latch positive edge triggered (rising edge of ) Master ection active low latch lave ection active high latch active high latch followed by active low latch negative edge triggered (falling edge of ) Master ection active high latch lave ection active low latch C.. troud, ept. of C, Auburn Univ.

5 Timing Considerations et-up time (t su )= minimum time input data must be valid before active edge of clock Hold time (t h )= minimum time input data must be held valid after active edge of clock Clock-to-output delay (t co )= maximum time before output data is valid with respect to active edge of clock t su t h t co et-up or Hold Time violation => metastability ( & go to intermediate voltage values which are eventually resolved to an unknown state) et-up & Hold Time violations in a vector set referred to as clock-data races C.. troud, ept. of C, Auburn Univ.

6 Timing Considerations To verify that a sequential logic circuit will work at the specified clock frequency, f clk, we must consider the clock period, T p, the propagation delay, P del, of the worst case path through the combinational logic, as well as t su and t co of the flip-flops such that the following relationship holds: For paths from flip-flop outputs to flip-flop inputs: + t co + t su For paths from primary inputs to flip-flop inputs: + t su For paths from flip-flop outputs to primary outputs: + t co For paths from primary inputs to primary outputs: Timing analysis and timing simulation CA tools are typically used for this verification. C.. troud, ept. of C, Auburn Univ.

7 Good esign Practices Use single clock, single edge synchronous design techniques as much as possible Asynchronous interfaces lead to metastability (minimize the async interface & double clock data to reduce probability of metastability) Avoid asynchronous presets & clears on FFs (use sync presets & clears whenever possible) O NOT construct a FF from two level sensitive latches of the same type with an inverter on the clock input to one latch active low latch active low latch O NOT gate clocks!!! Create clock enabled FFs via a MUX to feed back current data BA esign 0 1 CN CN BA esign GOO esign Active high clock enable (CN) C.. troud, ept. of C, Auburn Univ.

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