SetReset (SR) Latch


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1 eteset () Latch Asynchronous Level sensitive crosscoupled Nor gates active high inputs (only one can be active) + + Function eset et ? 0? Indeterminate crosscoupled Nand gates active low inputs (only one can be active) + + Function ? 1? Indeterminate et eset 1 1 C.. troud, ept. of C, Auburn Univ.
2 nabled eteset () Latch Asynchronous Level sensitive crosscoupled Nor gates active high inputs ( & cannot be active) + + Function 0 x x eset et ? 0? Indeterminate crosscoupled Nand gates active low inputs ( & cannot be active) + + Function ? 1? Indeterminate et eset x x C.. troud, ept. of C, Auburn Univ.
3 Transparent Latch Asynchronous Level sensitive crosscoupled Nor gates active high enable () + Function 0 x Transparent Mode Transparent Mode crosscoupled Nand gates active low enable () + Function 1 x Transparent Mode Transparent Mode C.. troud, ept. of C, Auburn Univ.
4 FlipFlop ynchronous (also know as Masterlave FF) dge Triggered (data moves on clock transition) one latch transparent  the other in storage active low latch followed by active high latch positive edge triggered (rising edge of ) Master ection active low latch lave ection active high latch active high latch followed by active low latch negative edge triggered (falling edge of ) Master ection active high latch lave ection active low latch C.. troud, ept. of C, Auburn Univ.
5 Timing Considerations etup time (t su )= minimum time input data must be valid before active edge of clock Hold time (t h )= minimum time input data must be held valid after active edge of clock Clocktooutput delay (t co )= maximum time before output data is valid with respect to active edge of clock t su t h t co etup or Hold Time violation => metastability ( & go to intermediate voltage values which are eventually resolved to an unknown state) etup & Hold Time violations in a vector set referred to as clockdata races C.. troud, ept. of C, Auburn Univ.
6 Timing Considerations To verify that a sequential logic circuit will work at the specified clock frequency, f clk, we must consider the clock period, T p, the propagation delay, P del, of the worst case path through the combinational logic, as well as t su and t co of the flipflops such that the following relationship holds: For paths from flipflop outputs to flipflop inputs: + t co + t su For paths from primary inputs to flipflop inputs: + t su For paths from flipflop outputs to primary outputs: + t co For paths from primary inputs to primary outputs: Timing analysis and timing simulation CA tools are typically used for this verification. C.. troud, ept. of C, Auburn Univ.
7 Good esign Practices Use single clock, single edge synchronous design techniques as much as possible Asynchronous interfaces lead to metastability (minimize the async interface & double clock data to reduce probability of metastability) Avoid asynchronous presets & clears on FFs (use sync presets & clears whenever possible) O NOT construct a FF from two level sensitive latches of the same type with an inverter on the clock input to one latch active low latch active low latch O NOT gate clocks!!! Create clock enabled FFs via a MUX to feed back current data BA esign 0 1 CN CN BA esign GOO esign Active high clock enable (CN) C.. troud, ept. of C, Auburn Univ.
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