Lecture 11: Sequential Circuit Design


 Virginia Hunt
 4 years ago
 Views:
Transcription
1 Lecture 11: Sequential Circuit esign
2 Outline Sequencing Sequencing Element esign Max and Minelay Clock Skew Time Borrowing TwoPhase Clocking 2
3 Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in CL out CL CL Finite State Machine Pipeline 3
4 Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiberoptic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. 4
5 Sequencing Overhead Use flipflops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 5
6 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flipflop: edge triggered A.k.a. masterslave flipflop, flipflop, register Timing iagrams Transparent Opaque Edgetrigger Latch Flop (latch) (flop) 6
7 Latch esign Pass Transistor Latch Pros +Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s 7
8 Latch esign Transmission gate +No V t drop  Requires inverted clock 8
9 Latch esign Inverting buffer +Restoring + No backdriving + Fixes either X Output noise sensitivity Or diffusion input Inverted output 9
10 Latch esign Tristate feedback + Static Backdriving risk X Static latches are now essential because of leakage 10
11 Latch esign Buffered input + Fixes diffusion input + Noninverting X 11
12 Latch esign Buffered output + No backdriving X Widely used in standard cells + Very robust (most important)  Rather large  Rather slow (1.5 2 FO4 delays)  High clock loading 12
13 Latch esign atapath latch +smaller +faster  unbuffered input X 13
14 FlipFlop esign Flipflop is built as pair of backtoback latches X X 14
15 Enable Enable: ignore clock when en = 0 Mux: increase latch  delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 0 Latch Latch en en en Flop 1 0 en Flop Flop en 15
16 Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Reset Asynchronous Reset reset reset reset reset reset reset 16
17 Set / Reset Set forces output high when enabled Flipflop with asynchronous set and reset reset set reset set 17
18 Sequencing Methods Flipflops T c 2Phase Latches Pulsed Latches FlipFlops Flop Combinational Logic Flop 2Phase Transparent Latches Pulsed Latches 1 2 p Latch t pw p Latch T c /2 Combinational Logic t nonoverlap Latch Combinational Logic Combinational Logic HalfCycle 1 HalfCycle 1 t nonoverlap Latch p Latch 18
19 Timing iagrams Contamination and Propagation elays t pd Logic Prop. elay A Combinational Logic Y A Y t cd t pd t cd t pcq t ccq Logic Cont. elay Latch/Flop Clk> Prop. elay Latch/Flop Clk> Cont. elay Flop t setup t hold t pcq t pdq Latch > Prop. elay t ccq t cdq t setup t hold Latch > Cont. elay Latch/Flop Setup Time Latch/Flop Hold Time Latch t setup t hold t t ccq pcq t cdq t pdq 19
20 Maxelay: FlipFlops ( setup ) tpd Tc t + tpcq sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 20
21 Max elay: 2Phase Latches ( 2 ) tpd = tpd1+ tpd 2 Tc tpdq sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 21
22 Max elay: Pulsed Latches ( setup ) tpd Tc max tpdq, tpcq + t tpw sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p t pcq tpd tsetup T c t pw 1 (b) t pw < t setup 2 22
23 Minelay: FlipFlops 1 t t t CL cd hold ccq F1 2 F2 1 t ccq t cd 2 t hold 23
24 Minelay: 2Phase Latches t t t t t cd1, cd 2 hold ccq nonoverlap 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold 24
25 Minelay: Pulsed Latches tcd thold tccq + t 1 pw CL p L1 Hold time increased by pulse width 2 p L2 p t pw t hold 1 t ccq t cd 2 25
26 Time Borrowing In a flopbased system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latchbased system ata can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle 26
27 Time Borrowing Example (a) Latch Combinational Logic Latch Combinational Logic Latch Borrowing time across halfcycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Latch Combinational Logic Latch Combinational Logic Loops may borrow time internally but must complete within the cycle 27
28 How Much Borrowing? 2Phase Latches T borrow c setup + nonoverlap ( ) t t t L1 1 2 Combinational Logic 1 L2 2 1 Pulsed Latches 2 T c t nonoverlap t t t borrow pw setup T c /2 Nominal HalfCycle 1 elay t borrow t setup 2 28
29 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing 29
30 Skew: FlipFlops ( setup skew ) tpd Tc tpcq + t + t t t t + t cd hold sequencing overhead ccq skew 1 F1 1 t pcq Combinational Logic T c t pdq 2 t setup F2 t skew 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd 30
31 Skew: Latches 2Phase Latches ( 2 ) tpd Tc tpdq sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew T t t + t + t 2 ( ) c borrow setup nonoverlap skew Pulsed Latches cd hold pw ccq ( setup skew ) tpd Tc max tpdq, tpcq + t tpw + t t t + t t + t ( ) t t t + t sequencing overhead skew borrow pw setup skew 31 2
32 TwoPhase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2 phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) 32
33 Safe FlipFlop Past years used flipflop with nonoverlapping clocks Slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 2 1 X
34 Adaptive Sequencing esigners include timing margin Voltage Temperature Process variation ata dependency Tool inaccuracies Alternative: run faster and check for near failures Idea introduced as Razor Increase frequency until at the verge of error Can reduce cycle time by ~30% 34
35 Summary FlipFlops: Very easy to use, supported by all tools 2Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk 35
Lecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Minelay q Clock Skew q Time Borrowing
More informationSequential Circuits. Combinational Circuits Outputs depend on the current inputs
Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating
More informationLecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Minelay
More informationSequential Circuit Design
Sequential Circuit Design LanDa Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines
More informationWeste07r4.fm Page 183 Monday, January 5, 2004 1:39 AM. 7.1 Introduction
Weste07r4.fm Page 183 Monday, January 5, 2004 1:39 AM 7 7.1 Introduction The previous chapter addressed combinational circuits in which the output is a function of the current inputs. This chapter discusses
More informationLatch Timing Parameters. Flipflop Timing Parameters. Typical Clock System. Clocking Overhead
Clock  key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationLecture 7: Clocking of VLSI Systems
Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 TwoPhase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10  Clocking Note: The analysis
More informationIntroduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems
Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH
More informationTiming Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
More informationClocking. Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 Clocks 1
ing Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884  Spring 2005 2/18/05
More informationTopics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology
Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Twophase clocking. Testing of combinational (Chapter 4) and sequential (Chapter
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flipflops;
More informationL4: Sequential Building Blocks (Flipflops, Latches and Registers)
L4: Sequential Building Blocks (Flipflops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit  FSM A Sequential circuit contains: Storage
More informationSequential Logic Design Principles.Latches and FlipFlops
Sequential Logic Design Principles.Latches and FlipFlops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and FlipFlops SR Latch
More informationSequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
More informationCHAPTER 11 LATCHES AND FLIPFLOPS
CHAPTER 11 LATCHES AND FLIPFLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 SetReset Latch 11.3 Gated D Latch 11.4 EdgeTriggered D FlipFlop 11.5 SR FlipFlop
More informationIntroduction to CMOS VLSI Design
Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, AddisonWesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration
More informationLecture 10: Latch and FlipFlop Design. Outline
Lecture 1: Latch and FlipFlop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flipflops
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationLecture3 MEMORY: Development of Memory:
Lecture3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More information路 論 Chapter 15 SystemLevel Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 SystemLevel Physical Design Dept. of Electronic Engineering National ChinYi University of Technology Fall 2007 Outline Clocked Flipflops CMOS
More informationChapter 2 Clocks and Resets
Chapter 2 Clocks and Resets 2.1 Introduction The cost of designing ASICs is increasing every year. In addition to the nonrecurring engineering (NRE) and mask costs, development costs are increasing due
More informationDesign Verification & Testing Design for Testability and Scan
Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing
More informationECE380 Digital Logic
ECE38 igital Logic FlipFlops, Registers and Counters: FlipFlops r.. J. Jackson Lecture 25 Flipflops The gated latch circuits presented are level sensitive and can change states more than once during
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationModeling Sequential Elements with Verilog. Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 41 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationClass 11: Transmission Gates, Latches
Topics: 1. Intro 2. Transmission Gate Logic Design 3. XGate 2to1 MUX 4. XGate XOR 5. XGate 8to1 MUX 6. XGate Logic Latch 7. Voltage Drop of nch XGates 8. nch Pass Transistors vs. CMOS XGates
More informationTopics. Flipflopbased sequential machines. Signals in flipflop system. Flipflop rules. Latchbased machines. Twosided latch constraint
Topics Flipflopbased sequential machines! Clocking disciplines. Flipflop rules! Primary inputs change after clock (φ) edge.! Primary inputs must stabilize before next clock edge.! Rules allow changes
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationSetReset (SR) Latch
eteset () Latch Asynchronous Level sensitive crosscoupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0? 0? Indeterminate crosscoupled Nand gates
More informationCSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap 5, App. A& B) Number representations Boolean algebra OP and PO Logic
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationMaster/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
More informationTheory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
More information. MEDIUM SPEED OPERATION  8MHz (typ.) @ . MULTIPACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE
HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE. MEDIUM SPEED OPERATION  8MHz (typ.) @ CL = 50pF AND DDSS = 10. MULTIPACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RES
More informationCDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch EdgeTriggered D FlipFlop (FF) SR FlipFlop (FF) JK FlipFlop (FF) T FlipFlop
More information7. Latches and FlipFlops
Chapter 7 Latches and FlipFlops Page 1 of 18 7. Latches and FlipFlops Latches and flipflops are the basic elements for storing information. One latch or flipflop can store one bit of information. The
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit A Sequential circuit contains: Storage elements:
More informationChapter 9 Latches, FlipFlops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, FlipFlops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationThe enable pin needs to be high for data to be fed to the outputs Q and Q bar.
of 7 Type flipflop (Toggle switch) The type flipflops are used in prescalar/divider circuits and frequency phase detectors. Figure shows how the flipflop (latch) can be made using input logic circuits
More informationLayout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More information74LS193 Synchronous 4Bit Binary Counter with Dual Clock
74LS193 Synchronous 4Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4bit binary counter. Synchronous operation is provided by having all flipflops
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationCS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on
CS 61C: Great Ideas in Computer Architecture Finite State Machines Instructors: Krste Asanovic & Vladimir Stojanovic hbp://inst.eecs.berkeley.edu/~cs61c/sp15 1 Levels of RepresentaKon/ InterpretaKon High
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationIEEE. Proof. INCREASING circuit speed is certain to remain the major. DualEdge Triggered Storage Elements and Clocking Strategy for LowPower Systems
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 5, MAY 2005 1 DualEdge Triggered Storage Elements and Clocking Strategy for LowPower Systems Nikola Nedovic, Member,, and Vojin
More informationWiki Lab Book. This week is practice for wiki usage during the project.
Wiki Lab Book Use a wiki as a lab book. Wikis are excellent tools for collaborative work (i.e. where you need to efficiently share lots of information and files with multiple people). This week is practice
More informationEE552. Advanced Logic Design and Switching Theory. Metastability. Ashirwad Bahukhandi. (Ashirwad Bahukhandi) bahukhan@usc.edu
EE552 Advanced Logic Design and Switching Theory Metastability by Ashirwad Bahukhandi (Ashirwad Bahukhandi) bahukhan@usc.edu This is an overview of what metastability is, ways of interpreting it, the issues
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationCounters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flipflop values themselves, serves as the output. The output value increases by one on each clock cycle.
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. PuJen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits PuJen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationDigital Fundamentals
igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage
More informationECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly
More informationChapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
More informationDATA SHEET. HEF40193B MSI 4bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
More informationFlipFlops and Sequential Circuit Design. ECE 152A Winter 2012
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationFlipFlops and Sequential Circuit Design
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationDecimal Number (base 10) Binary Number (base 2)
LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be
More informationDM74LS193 Synchronous 4Bit Binary Counter with Dual Clock
September 1986 Revised March 2000 DM74LS193 Synchronous 4Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4bit binary counter. Synchronous operation
More informationDM9368 7Segment Decoder/Driver/Latch with Constant Current Source Outputs
DM9368 7Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7segment decoder driver incorporating input latches and constant current output circuits
More informationDIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
More informationPowerPC Microprocessor Clock Modes
nc. Freescale Semiconductor AN1269 (Freescale Order Number) 1/96 Application Note PowerPC Microprocessor Clock Modes The PowerPC microprocessors offer customers numerous clocking options. An internal phaselock
More informationDM74LS169A Synchronous 4Bit Up/Down Binary Counter
Synchronous 4Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry lookahead for cascading in highspeed counting applications. Synchronous operation
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate Kmaps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More informationHCC/HCF4027B DUALJK MASTERSLAVE FLIPFLOP
DUALJK MASTERSLAVE FLIPFLOP. SETRESET CAPABILITY STATIC FLIPFLOP OPERATION  RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER HIGH OR LOW MEDIUM SPEED OPERATION  16MHz (typ. clock toggle rate
More informationNAME AND SURNAME. TIME: 1 hour 30 minutes 1/6
E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 20052006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June
More informationTIMINGDRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING
TIMINGDRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation
More informationMM74HC4538 Dual Retriggerable Monostable Multivibrator
MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicongate CMOS technology. They feature
More informationCS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flipflops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationDigital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
More informationS. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India
Power reduction on clocktree using Energy recovery and clock gating technique S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Abstract Power consumption of
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More information8254 PROGRAMMABLE INTERVAL TIMER
PROGRAMMABLE INTERVAL TIMER Y Y Y Compatible with All Intel and Most Other Microprocessors Handles Inputs from DC to 10 MHz 8 MHz 8254 10 MHz 82542 Status ReadBack Command Y Y Y Y Y Six Programmable
More informationTRUE SINGLE PHASE CLOCKING BASED FLIPFLOP DESIGN
TRUE SINGLE PHASE CLOCKING BASED FLIPFLOP DESIGN USING DIFFERENT FOUNDRIES Priyanka Sharma 1 and Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department
More informationSequential 4bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationDIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS
More informationDM74LS112A Dual NegativeEdgeTriggered MasterSlave JK FlipFlop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000 DM74LS112A Dual NegativeEdgeTriggered MasterSlave JK FlipFlop with Preset, Clear, and Complementary General Description This device contains two independent negativeedgetriggered
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIPFLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationTRIPLE D FLIPFLOP FEATURES DESCRIPTION PIN NAMES BLOCK DIAGRAM
TRIPLE D FLIPFLOP FEATURES DESCRIPTION Max. toggle frequency of 800MHz Differential outputs IEE min. of 80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = 4.2V to 5.5V Voltage
More information2/4, 4/5/6 CLOCK GENERATION CHIP
2/4, 4/5/6 CLOCK GENERATION CHIP FEATURES 3.3V and 5V power supply option 50ps outputtooutput skew 50% duty cycle outputs Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input
More informationAlpha CPU and Clock Design Evolution
Alpha CPU and Clock Design Evolution This lecture uses two papers that discuss the evolution of the Alpha CPU and clocking strategy over three CPU generations Gronowski, Paul E., et.al., High Performance
More informationRegister File, Finite State Machines & Hardware Control Language
Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework
More informationCD4027BC Dual JK Master/Slave FlipFlop with Set and Reset
October 1987 Revised March 2002 CD4027BC Dual JK Master/Slave FlipFlop with Set and Reset General Description The CD4027BC dual JK flipflops are monolithic complementary MOS (CMOS) integrated circuits
More informationDM54161 DM74161 DM74163 Synchronous 4Bit Counters
DM54161 DM74161 DM74163 Synchronous 4Bit Counters General Description These synchronous presettable counters feature an internal carry lookahead for application in highspeed counting designs The 161
More informationTwoPhase Clocking Scheme for LowPower and High Speed VLSI
International Journal of Advances in Engineering Science and Technology 225 www.sestindia.org/volumeijaest/ and www.ijaestonline.com ISSN: 23191120 TwoPhase Clocking Scheme for LowPower and High Speed
More informationNOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual InLine Package.
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo6
More informationCounters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of ModuloN ripple counter, UpDown counter, design of synchronous counters with and without
More information