# DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

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1 DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIP-FLOPS 1st year BSc course 2nd (Spring) term 2012/ ELEMENTARY SEUENTIAL CIRCUITS Combinational networks: can be constructed from elementary combinational circuits i.e. form gates. Sequential (synchronous and asynchronous) networks: can be constructed from elementary sequential circuits. Elementary sequential circuits: left alone, the have only one they can handle only very simple logic tasks, they have only one secondary (state) variable. Therefore they have only two states and one or two control inputs. Usual names: bistable (multivibrator), memory/storage element, flip-flop. 2 1

2 FLIP-FLOPS Flip-flop, latch or bistable multivibrator is an electronic circuit which has two stable states. It is capable to function as a memory. A flip-flop is controlled by one or two control signals and/or a gate or clock signal. The output often includes the complement as well as the normal output. Sometimes they have separate auxiliary clear and load/set/preset inputs too. ELEMENTARY SYNHRONOUS STORAGE CELL (FLIP-FLOP) The logic control does not make any effect at the output, until the clock pulse starts the change of the internal state of FF. This is a transient process during which the logic control of the circuit must no be changed, Let the circuit be in peace! The duration of a clock period must be longer then the duration of the longest transient. 4 2

3 TIMING CONTROL 5 FLIP-FLOPS The most important flip-flops are the following: R-S (or S-R) flip-flop J-K flip-flop T flip-flop D-G flip-flop D flip-flop All flip-flops listed above can function in synchronous or clocked mode, the R-S and D flip-flops can operate in asynchronous mode too. The behaviour of a particular type can be described by truth/characteristic table and the characteristic equation, which gives the next output in terms of the input control signals and the current output. 3

4 OPERATION OF FLIP-FLOPS -The change of state of asynchronous flip-flops occurs directly as a response to the change of the input/control variable(s), after the appropriate time delay of the circuit. -The change of state of synchronous (clock controlled) flipflops occurs only when the synchronizing signal (clock) arrives tot heir appropriate input. 7 FLIP-FLOPS: STATIC AND DYNAMIC CONTROL The control of flip-flops can be either static or dynamic. Static: appropriate logic 0 and/or 1 levees should be applied to the static control inputs to initiate the state changes. Dynamic: the change of state of the flip-flop occurs due the change in the appropriate direction (1 0 or 0 1 transition) of the signal applied to the dynamic control input (edgetriggered). 8 4

5 FLIP-FLOPS: NOTATIONS D D D D CK CK >CK >CK CK: clock (a) (b) (c) (d) (a) CK=1, (b) CK=0 levels activate the information transfer (c) CK rising edge, (d) CK falling edge activates the FF. Usualy S (set, PR preset), R (reset,clr clear) inputs and # output is also provided. 9 RS FLIP-FLOP: INTRODUCTION The SR (set/reset) flip-flop is one of the simplest flip/flops used in digital systems. It can be realized/implemented by direct feedback of a combinational circuit, i.e. with asynchronous sequential circuit. Some features: - Two control inputs: Reset és Set - Two (complementary) outputs - Three allowed (defined)and one forbidden (undefined) outputs - The allowed states are stable - The forbidden state can be unastable 10 5

6 RESET-SET (R-S) FLIP-FLOP (1) Simple truth table R S n n X SET loading, RESET clearing, independently of the pervious state. Defined operation: S = 1 sets the FF state to 1, and it holds this state even after the termination of control. R = 1 stes the FF state to 0, and it holds this state even after the termination of control. If S and R are simultaneously 0 the state of the FF does not change, it holds its previous state. If S and R are simultaneously 1, the FF functioning is not defined, therefore this control combnination is logically forbidden. 11 RS FLIP-FLOP: CASE OF R=S=1 For the R=S=1 input combination the output is not defined, so this input combination is not allowed. However a given circuit implementation will produce a certain, mostly well define output state for this input. E.g. The NOR gate based circuit will give 0 logic level on both (direct and complementary) output, the NAND based circuit will give logic level 1 on both output. In these cases the complementary relation between the two outputs is not fulfilled

7 R-S FLIP-FLOP (2) n-edik (n+1)-edik Extended truth table ütem R S n n does not change does not change toggles does not change does not change toggles X undefined X undefined 13 R-S FLIP-FLOP: NOR GATE IMPLEMENTATION is on R side! NOR gate: 1 on any input forces the output to 0! 14 7

8 S-R (SET-RESET) FLIP-FLOP: TIMING BEHAVIOUR The S-R flip-flop is an active high (positive logic) device. INVERSE R-S FLIP-FLOP R S n X n The inverse RS flip-flop is controlled by the 0 levels. Implementation: two cross coupled NAND gates. For the logically undefined input combination both NAND gates give 1 on their outputs. 16 8

9 RS FLIP-FLOP/INVERSE RS FLIP-FLOP is on S side! S R NAND gate: 0 on anyi nput forces the output to 1! 17 NOR S-R NAND S-R CONVERSION Active High NOR Implementation. Push Bubbles (DeMorgan s) Rearrange Bubbles Convert from Bubbles to Active Low Signal Names 18 9

10 R-S FLIP-FLOP: STATE TABLE AND TRANSITION DIAGRAM n+1 SR n X X 1 SR 00,01 00, No oscillation can develop in any of the column, the operation can be defined both in asynchronous and synchronous mode. (Red: stable states.) 19 ASYNCHRONOUS R-S FF IMPLEMENTATION WITH COMBINATIONAL NETWORK The state transition table can be considered as a Karnaugh table S 0 0 X 1 n 1 0 X 1 R S R y _ n+1 = S + R n f(s,r,y) Y Z n n

11 AND-OR GATE IMPLEMENTATION: LOGIC DIAGRAM _ n+1 = S + R n characterisitc eqiation implemented: S R 1 _ R & 1 (Y) n+1 (Z) n (y) 21 TRANSFORMATION TO NAND-NAND REALIZATION Transformation according DeMorgan s law S R 1 _ R & & 22 11

12 TRANSFORMATION TO NAND-NAND REALIZATION Transformation according DeMorgan s law and rearranging/redrawing the circuit: S S 1 & R 1 & & R 1 & _ 23 SR FLIP-FLOP The problem of logically undefined state (S = R =1) can be handled by using an additional inverter to generate ` from (for NAND gate realization): S 1 _ R For the excitation SR =1 the output will be = 1, i.e. the S input has the priority. 12

13 R-S FLIP-FLOP: EMPHASIS - The RS flip-flop is typically an asynchronous circuit. - RS flip-flops are nor produced/used for/in networks, because other flip-flop types are more effective (they don t have forbidden states). - However synchronous flip-flops usually contain asynchronous, static zeroing (RESET) and loading (SET ior PRESET) facilities. - The RS flip-flop is the basic unit of semiconductor memories (SRAM, static random access memory). 25 RS FLIP-FLOP: ENHANCEMENTS Solution: State change initiated by clock: gated RS flip-flop JK flip-flop D flip-flop 26 13

14 GATED/CLOCK-CONTROLLED RS FLIP-FLOP The gate input can also accept a CLOCk signal: synchronous operation 27 GATED RS FLIP-FLOP State change : 0 1 transition on G S & & G 1 R n+1 = SG + RG n & & 28 _ 14

15 JK FLIP-FLOP (1) The JK flip-flop augments the behaviour of the SR flip-flop by interpreting the S = R = 1 conditions as a flip ( toggle ) command: J K next Comment 0 0 prev hold state reset set _ 1 1 prev toggle J-K FLIP-FLOP (2) In a certain respect it is an enhanced version of the RS FF. Logic/control fucntion is defined to the originally not-allowd control combination of the RS FF: SR-JK corresponence: S J R K 30 15

16 Simple truth table J-K FLIP-FLOP (3) J K n n _ 1 1 n Defined functioning: J = 1 K = 0 sets FF state to 1, K = 1 J = 0 sets FF state to 0, If J and K is simultaneously 0 the state does not change. If J and K is simultaneously 1 the state of the FF is complemented. 31 J-K FLIP-FLOP (4) n-th (n+1)-th Extended thuth table state J K n n holding state holding state zeroing (set 0) zeroing (set 0) setting (set 1) setting (set 1) complementing complementing 32 16

17 J-K FLIP-FLOP: STATE TABLE ANF GRAPH n+1 JK n JK 00,01 00,10 10, ,11 No stable state exist in the JK= 1 column. The JK FF can only be operated as a synchronous circuit. Cannot operate without gating/clocking signal. 33 J-K FLIP-FLOP: CHARACTERISTC EUATION Implementation in principle J n K _ n+1 = J n + K n + J K The third term in the equation is necessary for the elimination of race hazards 17

18 J-K FLIP-FLOP: TIME DIAGRAM 35 JK FF BUILT ON THE BASIS OF RS FF The JK flip-flop can be built fro gated RS FF of the R input is gated with the output, and the S input is gated with the / output. The indicated gatinb/feedback ensures the R = S = 1 input state would not occur! 36 18

19 JK FF OPERATION The operation of JK FF can be demonstrated by its characteristic equation. The original RS flip-flop J _ n+1 = S + R n Applying the feedback _ K S = J n and R = K n n+1 = S + R n = J n + (K + n ) n = J n + K n. E. D. 37 GATED JK FLIP FLOP J G K 38 19

20 GATED JK FLIP FLOP Similarly as in the case of gated RS FF in the case of gated JK FF the control signals exert their influence only when the gate signal is 1. If the width of the gating pulse on input G is less than the signal propagation time through the two gates, then for J = K = 1 the FF will change its state only once in response to the gate signal. On the other hand a too short gate signal width can result in an uncertain operation, because the too short signals might not push the FF int the correct state. 39 MASTER-SLAVE FLIP-FLOP The JK flip-flops used in practice mostly operate on the basis of master-slave principle. The master-slave flip-flops consist of two elementary storage cells, the first is the master, the second is the slave. The principle of operation, and its realization will be demonstrated on the example of RS flip-flop

21 TWO-CYCLE (MASTER-SLAVE) STORAGE CELL (FLIP-FLOP) PRINCIPLE The two switches operate in opposite cycle! Input signal Clock Input (master) flip-flop Output (slave) flip-flop Output Clock signal waveform H level minimum L level maximum time 41 TWO-CYCLE (MASTER-SLAVE) RS FF Input (master) flip-flop Output (slave) flip-flop CLK CLK 42 21

22 THE MASTER-SLAVE JK FLIP-FLOP The feedback ensuring the JK operation goes form the outputs of the slave FF to the control inputs of the master FF! T (TOGGLE) FLIP-FLOP The T (TOGGLE, Hungarian:~ kb. ideoda billen) flip-flop is FF with one control input. The active control of T (HIGH level) excites the complementing of the FF s state. It can be derived from the J-K FF by joining (interconnecting) the J and K inputs.. T J K _ 44 22

23 OPERATION OF T FLIP-FLOP: STATE TABLE AN DIAGRAM T 0 1 n n+1 T No stable state exist in the T = 1 column. The T flip-flop can only be a synchronous sequential network. 45 T FLIP-FLOP: CHARACTERISTIC EUATION T n n n+1 = T n + T n = T n

24 T FLIP-PLOP T flip-flops do not really exist, constructed from JK or D FFs. Usually best choice for implementing counters. To create a T-FF using a D: Add a feedback connection that makes the input signal D equal either the value of or under the control of the signal T. D FLIP-FLOP (1) The state of the output of the D (DELAY) flip-flop in the next, (n+1)-th state will be equal to the state of the D control input in the pevious, n- th state: n+1 = D n 48 24

25 D FLIP-FLOP (2) Truth table and characteristic equation n-th (n+1)-th state n+1 = D D n n In fact the state in the (n+1)-th state in fac t will nt depend on what was the state of the FF in the n-th state! The D flip-flop does not remember its previous stater 49 D FLIP-FLOP: STATE TABLE AND STATE TRANSITION DIAGRAM D 0 1 n n+1 Characteristic equation: n+1 = D D

26 A D FLIP-FLOP (3) -The D flip-flop is mostly used to as a component in storage registers. -E.g.to store the value displayed by a digital instruments, till the value of the new reading arrives. 51 D FLIP-FLOP WITH CLOCK Operation of D (DELAY) flip-flop with synchronizing clock. If there is no clock signal (C=0) the output does not change ( n = n-1 ), if there is a clock signal (C=1) the output will take the actual value of the input, i.e. n = D

27 GATED D FLIP-FLOP n n G G D D _ n+1 = D G + G n + D n 3rd loop: hazard elimination Operation can be asynchronous or synchronous. TIME DIAGRAM OF GATED FLIP-FLOP 54 27

28 CHARACTERISTIC EUATIONS OF FLIP-FLOPS: A SUMMARY RS JK T _ n+1 = S + R n _ n+1 = J n + K n + J K n+1 = T n + T n = T n D n+1 = D n _ D-G n+1 = D G +G n + D n Note: The third terms in the equation of JK and D-G flip-flops serve for the elimination of race hazards EXCITATION TABLES OF FLIP-FLOPS n n+1 R S J K D T 0 0 x 0 0 X X X X X The excitation table lists the required inputs for a given change of state, i.e. the input conditions that will cause the transition form a given present state to the next state. The excitation table is required and is used in the design process. 28

29 SUMMARY OF FLIP-FLOP TYPES S=R=1 not allowed Most versatile type Most simple Gated (DG) Copies input to output Complements output if activated STATE TRANSITION DIAGRAMS: SUMMARY SR flip-flop JK flip-flop D flip-flop T flip-flop 58 29

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