WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

Transcription

1 WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1

2 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits and Systems Page 2

3 Characteristic tables and equations for FFs We can describe the behavior of a flip-flop via a characteristic table. The characteristic table shows what the next flip-flop output value will be given the current flip-flop input value after the clock makes its active edge transition. We can also write this as a characteristic equation: ECE124 igital Circuits and Systems Page 3

4 Toggle flip-flops (TFF) Another type of flip-flop that has a different behavior when compared to a FF. Symbol for a positive edge-triggered TFF: T Symbol for a negative edge-triggered TFF: T ECE124 igital Circuits and Systems Page 4

5 Characteristic tables and equations for TFFs The characteristic table for the TFF: The characteristic equation for the TFF: So with a TFF, the output toggles (or flips) its value if the input is T=1, otherwise it remains the same. ECE124 igital Circuits and Systems Page 5

6 Making a TFF from a FF We can actually build a TFF using a FF and a 2-input XO gate. T T CLOCK ECE124 igital Circuits and Systems Page 6

7 JK flip-flops (JKFF) Another type of flip-flop that has different behavior compared to a FF or to a TFF. Positive edge-triggered JKFF: J K Negative edge-triggered JKFF: ECE124 igital Circuits and Systems Page 7

8 Characteristic tables and equations for JKFFs The characteristic table for the JKFF: We can derive the characteristic equation for the JKFF (I find it easy to explain via a K- Map): JK (t) ECE124 igital Circuits and Systems Page 8

9 Making a JKFF from a FF We can actually build a JKFF using a FF and some other gates. J J K CLOCK K ECE124 igital Circuits and Systems Page 9

10 Timing analysis with flip-flops There are some important things to understand when we go to actually make and implement a circuit with flip-flops. In reality, it takes time for gates to change their output values according to the input values i.e., there are propagation delays due to resistance, capacitance, etc. Changes in flip-flop outputs occur at the active clock edge. There are three timing parameters that are especially important: Setup Time (TSU). Hold Time (TH). Clock-To-Output Time (TCO). ECE124 igital Circuits and Systems Page 10

11 efinitions for timing analysis of flip-flops Setup Time (TSU): The setup time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) PIO to the arrival of the active clock edge. Hold Time (TH): The hold time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) AFTE the arrival of the active clock edge. Clock-To-Output (TCO): The clock-to-output time of a flip-flop is the amount of time it takes for the output to become stable (at its new value) AFTE the arrival of the active clock edge. ECE124 igital Circuits and Systems Page 11

12 Comments If these timing specifications are not met, then it is possible that the flip-flop will not behave as expected. That is, if we don t observe setup and hold times at the data inputs, then our output might not change as expected. That is, if we don t wait long enough (clock-to-output time) for the output to change, then we might use an incorrect value. If we violate any of these timing parameters, then we have a timing violation. These timing parameters (as we will see later) have an influence on how fast we can clock a circuit. ECE124 igital Circuits and Systems Page 12

13 Illustration of timing parameters (for a FF) TSU TH TCO CLOCK should not change in this interval not stable (trustworthy) until this interval ends ECE124 igital Circuits and Systems Page 13

14 egisters A single FF stores one bit A group of n FFs stores n-bits and is called an n-bit register. I0 A0 Illustration: When clear=0, all flip-flop outputs are forced to zero (active low reset). I1 A1 When clear=1, the rising edge of the clock (the active clock edge), results in the 4-bit input transferred to register output. I2 A2 I3 A3 clock clear ECE124 igital Circuits and Systems Page 14

15 Parallel loads (1) We might want to prevent the transfer of data from input to output even though the active clock edge arrives we want the register to HOL ITS CUENT VALUE. We can do this by feeding the register outputs back to the inputs and adding some additional logic to control the register operation. ECE124 igital Circuits and Systems Page 15

16 Parallel loads (2) When load=1, the data inputs reach the -input of the flip-flop. When the active clock edge arrives, the data gets transferred, or loaded, to the register output. When load=0, the data output of each flip-flop is fed back to its -input. I0 I1 A0 A1 When the active clock edge arrives, the data input gets transferred to the register output, but since the values are the same for all flip-flops, the register holds its current value. I2 I3 A2 A3 load clock clear ECE124 igital Circuits and Systems Page 16

17 Shift registers Might want a register that can shift data serially in a direction This type of register is called a shift register. Illustration of a 4-bit shift register. serial in serial out clock clear As active clock edges arrive, the data present at the serial input gets transferred towards the serial output so, data gets shifted to the right one bit at a time as clock edges arrive. ECE124 igital Circuits and Systems Page 17

18 Comment Whenever we would like to add an operation to our register, we are simply placing a MUX in from of each FF in order to direct the correct information to the FF inputs in order to obtain the correct operation. ECE124 igital Circuits and Systems Page 18

19 Universal shift registers (1) Perhaps we want a more general circuit e.g., we want to be able to clear the register, load the register, and perform both a shift right and a shift left operation. ECE124 igital Circuits and Systems Page 19

20 Universal shift registers (2) 4-bit register capable of multiple operations (use multiplexers instead of AN/O gates at FF inputs): data in (rshift) I A0 I A1 I A2 I A3 data in (lshift) c1 c0 clock clear ECE124 igital Circuits and Systems Page 20

21 Universal shift registers (3) Has an asynchronous clear signal Has a clock signal Has data inputs for parallel load Has data inputs for both left and right shifts Has two control inputs that determine behavior: ECE124 igital Circuits and Systems Page 21

22 Counters A counter is a register whose outputs go through a prescribed sequence of states upon the arrival of the active edge of some triggering signal (e.g., like a clock). The prescribed sequence of states, or register outputs, can be anything. Counters can come in two varieties asynchronous or synchronous. ECE124 igital Circuits and Systems Page 22

23 ipple counters ipple counters consist of a series of flip-flops where the output of one flip-flop is used (somehow) as the clock for the next flip-flop. It is the lack of a common clock signal for each flip-flop that makes the counter asynchronous. ECE124 igital Circuits and Systems Page 23

24 Binary ripple counter (1) A type of ripple counter that has n-bits, and can count in binary from 0 to 2 n -1 and repeat. E.g., count sequence for 4-bits: ECE124 igital Circuits and Systems Page 24

25 Binary ripple counter (2) We can make a binary ripple counter easily via observation 1 count T A0 A 0 always flips A 1 flips with A 0 goes 1 -> 0 T A1 A 2 flips with A 1 goes 1 -> 0 Etc So, the i-th bit complements the (i+1)-th bit when it goes 1 -> 0. T A2 Binary ripple counter easily done with TFFs. T A3 clear ECE124 igital Circuits and Systems Page 25

26 Up and down binary ripple counters Up counters count in the sequence 0, 1, 2,, 2 n -1 and repeats. own counters count in the sequence 2 n -1,, 2, 1, 0 and repeats. Should be able to take our previous example and construct a binary ripple down counter ECE124 igital Circuits and Systems Page 26

27 ipple counter delays ecall: Flip-flops have clock-to-output times (it takes time for the output to change once the clock signal arrives on the flip-flop). Because of this, it can take a lot of time for the higher order bits of a ripple counter to change (remember that the i-th bit output is used as the clock for the (i+1)-th bit). count A0 A1 A2 A3 transition time due to clock-to-output times So, the FF outputs do not change at the same time due to the ripple effect in the clock inputs. We would like FF outputs to change simultaneously. This is why we prefer to design synchronous counters. ECE124 igital Circuits and Systems Page 27

28 Synchronous counters ifferent from ripple counters in that (the same) clock pulses are applied to the clock inputs of all flip-flops simultaneously. Flip-flop outputs then change simultaneously. ECE124 igital Circuits and Systems Page 28

29 Example: Synchronous Binary Up Counter Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count. Observation: A 0 is always toggling, A 1 toggles if A 0 is 1, A 2 toggles if A 0, A 1 are 1, A 3 toggles if A 0, A 1, A 2 are 1 Observations motivate the use of TFF ECE124 igital Circuits and Systems Page 29

30 Example: Synchronous Binary Up Counter Synchronous 4-bit binary up counter with enable using TFF: enable T A0 T A1 T A2 T A3 clock clear next stage ECE124 igital Circuits and Systems Page 30

31 Example: Synchronous Binary own Counter Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count. Observation: A 0 is always toggling, A 1 toggles if A 0 is 0 A 2 toggles if A 0, A 1 are 0, A 3 toggles if A 0, A 1, A 2 are 0 Observations motivate the use of TFF ECE124 igital Circuits and Systems Page 31

32 Example: Synchronous Binary own Counter Synchronous 4-bit binary down counter with enable using TFF: down T A0 T A1 T A2 T A3 clock clear next stage ECE124 igital Circuits and Systems Page 32

33 Example: Synchronous Binary Up/own Counter Can combine the up and down counter to get an up/down counter (re-use previously built circuits!) Trick is getting correct input to the FF in order to perform correct operation. Consider the following control inputs which determine circuit behaviour: ECE124 igital Circuits and Systems Page 33

34 Example: Synchronous Binary Up/own Counter Have both logic for up count and down count; up has priority (it disables down). ECE124 igital Circuits and Systems Page 34

35 Example: Synchronous Binary Up/own Counter With Parallel Load Often useful to have a counter that we can load with a starting count. This requires adding another control line (load) and data inputs: ECE124 igital Circuits and Systems Page 35

36 Example: Synchronous Binary Up/own Counter With Parallel Load load up down L U I0 T A0 I1 T A1 I2 T A2 I3 T A3 clock clear ECE124 igital Circuits and Systems Page 36

37 Comments All of the previous counters could have been built using FF or JKFF. esigning counters that perform multiple operations involves: Making sure that the correct inputs get to the FF inputs in order to perform the specific function; and The logic feeding the FF input will cause the FF output to change appropriately. If the control signals and operations have priority, we need to make sure that the control signal priority disables the operation due to other control lines (e.g., parallel load turns off up/down count signals. ECE124 igital Circuits and Systems Page 37

38 Symbols We might have different symbols to represent counters: E.g., I0 I1 I2 I3 CL UP A0 A1 A2 A3 ECE124 igital Circuits and Systems Page 38

39 Modulo counters Sometimes we don t want to count through the entire sequence of binary numbers. E.g., we might want to count 0, 1,,2,, 10 and repeat. (This is effectively a modulo- 10 counter). We could design such a counter using synchronous circuit design principles, but we could also attempt something a bit trickier We can use additional circuitry to detect our maximum count number and use a parallel load to restart the counting. ECE124 igital Circuits and Systems Page 39

40 Modulo counter build from a binary counter building block E.g., design a counter that counts 0, 1,,2,, 10 and repeats. CLK I0 A0 I1 A1 I2 A2 I3 A3 CL UP LOA ECE124 igital Circuits and Systems Page 40

41 Some Other Types of Counters: ing counters An n-bit counter in which only one output is high at any given time. E.g., Can illustrate with a timing diagram for 4-bits: CLK A0 A1 A2 A3 Outputs like this useful to generate timing signals that indicate an order of operation in another circuit block. ECE124 igital Circuits and Systems Page 41

42 Some Other Types of Counters: ing counters Can make an n-bit ring counter with a shift register. E.g., 4-bit ring counter: A0 A1 A2 A3 S clear clk To generate n non-overlapping timing signals, we need a shift register with n flip-flops. ECE124 igital Circuits and Systems Page 42

43 Some Other Types of Counters: ing counters Can also use a combination of a counter and a decoder. E.g., 4-bit ring counter with 2-bit counter and decoder. 1 CL A0 A1 x y 0 1 A0 A1 CLK 1 COUNT 2 3 A2 A3 2-bit counter 2-to-4 decoder ECE124 igital Circuits and Systems Page 43

44 Some Other Types of Counters: Switch-tail ring counters Consider the following 4-bit circuit: A0 A1 A2 A3 clear clk esembles a 4-bit ring counter, but complement of MSB fed back to LSB. ECE124 igital Circuits and Systems Page 44

45 Some Other Types of Counters: Switch-tail ring counters Count pattern can be determined: So, with n bits we get a count pattern of 2 n output states. ECE124 igital Circuits and Systems Page 45

46 Some Other Types of Counters: Johnson counters We can add additional detection circuitry in order to generate the disjoint timing signals like a ring counter. This results in a Johnson Counter. With a Johnson Counter, we can get 2 n non-overlapping timing signals using n flip-flops and some extra 2-input AN gates. ECE124 igital Circuits and Systems Page 46

47 Closing emarks Synchronous counters are nice because the counter outputs all change at the same time (according to the clock). We have only talked about some types of counters; e.g., Binary up/down counters; modulo counters. In general, counters are simply an example of a clocked sequential circuit. We can design any type of counter (e.g., any sequence of values we want) once we learn about clocked sequential circuit design (coming up in the course). E.g., we will see how to design a counter that counts 0, 3, 5, 4, 1, and repeats (if we wanted to). ECE124 igital Circuits and Systems Page 47