WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1"

Transcription

1 WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1

2 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits and Systems Page 2

3 Characteristic tables and equations for FFs We can describe the behavior of a flip-flop via a characteristic table. The characteristic table shows what the next flip-flop output value will be given the current flip-flop input value after the clock makes its active edge transition. We can also write this as a characteristic equation: ECE124 igital Circuits and Systems Page 3

4 Toggle flip-flops (TFF) Another type of flip-flop that has a different behavior when compared to a FF. Symbol for a positive edge-triggered TFF: T Symbol for a negative edge-triggered TFF: T ECE124 igital Circuits and Systems Page 4

5 Characteristic tables and equations for TFFs The characteristic table for the TFF: The characteristic equation for the TFF: So with a TFF, the output toggles (or flips) its value if the input is T=1, otherwise it remains the same. ECE124 igital Circuits and Systems Page 5

6 Making a TFF from a FF We can actually build a TFF using a FF and a 2-input XO gate. T T CLOCK ECE124 igital Circuits and Systems Page 6

7 JK flip-flops (JKFF) Another type of flip-flop that has different behavior compared to a FF or to a TFF. Positive edge-triggered JKFF: J K Negative edge-triggered JKFF: ECE124 igital Circuits and Systems Page 7

8 Characteristic tables and equations for JKFFs The characteristic table for the JKFF: We can derive the characteristic equation for the JKFF (I find it easy to explain via a K- Map): JK (t) ECE124 igital Circuits and Systems Page 8

9 Making a JKFF from a FF We can actually build a JKFF using a FF and some other gates. J J K CLOCK K ECE124 igital Circuits and Systems Page 9

10 Timing analysis with flip-flops There are some important things to understand when we go to actually make and implement a circuit with flip-flops. In reality, it takes time for gates to change their output values according to the input values i.e., there are propagation delays due to resistance, capacitance, etc. Changes in flip-flop outputs occur at the active clock edge. There are three timing parameters that are especially important: Setup Time (TSU). Hold Time (TH). Clock-To-Output Time (TCO). ECE124 igital Circuits and Systems Page 10

11 efinitions for timing analysis of flip-flops Setup Time (TSU): The setup time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) PIO to the arrival of the active clock edge. Hold Time (TH): The hold time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) AFTE the arrival of the active clock edge. Clock-To-Output (TCO): The clock-to-output time of a flip-flop is the amount of time it takes for the output to become stable (at its new value) AFTE the arrival of the active clock edge. ECE124 igital Circuits and Systems Page 11

12 Comments If these timing specifications are not met, then it is possible that the flip-flop will not behave as expected. That is, if we don t observe setup and hold times at the data inputs, then our output might not change as expected. That is, if we don t wait long enough (clock-to-output time) for the output to change, then we might use an incorrect value. If we violate any of these timing parameters, then we have a timing violation. These timing parameters (as we will see later) have an influence on how fast we can clock a circuit. ECE124 igital Circuits and Systems Page 12

13 Illustration of timing parameters (for a FF) TSU TH TCO CLOCK should not change in this interval not stable (trustworthy) until this interval ends ECE124 igital Circuits and Systems Page 13

14 egisters A single FF stores one bit A group of n FFs stores n-bits and is called an n-bit register. I0 A0 Illustration: When clear=0, all flip-flop outputs are forced to zero (active low reset). I1 A1 When clear=1, the rising edge of the clock (the active clock edge), results in the 4-bit input transferred to register output. I2 A2 I3 A3 clock clear ECE124 igital Circuits and Systems Page 14

15 Parallel loads (1) We might want to prevent the transfer of data from input to output even though the active clock edge arrives we want the register to HOL ITS CUENT VALUE. We can do this by feeding the register outputs back to the inputs and adding some additional logic to control the register operation. ECE124 igital Circuits and Systems Page 15

16 Parallel loads (2) When load=1, the data inputs reach the -input of the flip-flop. When the active clock edge arrives, the data gets transferred, or loaded, to the register output. When load=0, the data output of each flip-flop is fed back to its -input. I0 I1 A0 A1 When the active clock edge arrives, the data input gets transferred to the register output, but since the values are the same for all flip-flops, the register holds its current value. I2 I3 A2 A3 load clock clear ECE124 igital Circuits and Systems Page 16

17 Shift registers Might want a register that can shift data serially in a direction This type of register is called a shift register. Illustration of a 4-bit shift register. serial in serial out clock clear As active clock edges arrive, the data present at the serial input gets transferred towards the serial output so, data gets shifted to the right one bit at a time as clock edges arrive. ECE124 igital Circuits and Systems Page 17

18 Comment Whenever we would like to add an operation to our register, we are simply placing a MUX in from of each FF in order to direct the correct information to the FF inputs in order to obtain the correct operation. ECE124 igital Circuits and Systems Page 18

19 Universal shift registers (1) Perhaps we want a more general circuit e.g., we want to be able to clear the register, load the register, and perform both a shift right and a shift left operation. ECE124 igital Circuits and Systems Page 19

20 Universal shift registers (2) 4-bit register capable of multiple operations (use multiplexers instead of AN/O gates at FF inputs): data in (rshift) I A0 I A1 I A2 I A3 data in (lshift) c1 c0 clock clear ECE124 igital Circuits and Systems Page 20

21 Universal shift registers (3) Has an asynchronous clear signal Has a clock signal Has data inputs for parallel load Has data inputs for both left and right shifts Has two control inputs that determine behavior: ECE124 igital Circuits and Systems Page 21

22 Counters A counter is a register whose outputs go through a prescribed sequence of states upon the arrival of the active edge of some triggering signal (e.g., like a clock). The prescribed sequence of states, or register outputs, can be anything. Counters can come in two varieties asynchronous or synchronous. ECE124 igital Circuits and Systems Page 22

23 ipple counters ipple counters consist of a series of flip-flops where the output of one flip-flop is used (somehow) as the clock for the next flip-flop. It is the lack of a common clock signal for each flip-flop that makes the counter asynchronous. ECE124 igital Circuits and Systems Page 23

24 Binary ripple counter (1) A type of ripple counter that has n-bits, and can count in binary from 0 to 2 n -1 and repeat. E.g., count sequence for 4-bits: ECE124 igital Circuits and Systems Page 24

25 Binary ripple counter (2) We can make a binary ripple counter easily via observation 1 count T A0 A 0 always flips A 1 flips with A 0 goes 1 -> 0 T A1 A 2 flips with A 1 goes 1 -> 0 Etc So, the i-th bit complements the (i+1)-th bit when it goes 1 -> 0. T A2 Binary ripple counter easily done with TFFs. T A3 clear ECE124 igital Circuits and Systems Page 25

26 Up and down binary ripple counters Up counters count in the sequence 0, 1, 2,, 2 n -1 and repeats. own counters count in the sequence 2 n -1,, 2, 1, 0 and repeats. Should be able to take our previous example and construct a binary ripple down counter ECE124 igital Circuits and Systems Page 26

27 ipple counter delays ecall: Flip-flops have clock-to-output times (it takes time for the output to change once the clock signal arrives on the flip-flop). Because of this, it can take a lot of time for the higher order bits of a ripple counter to change (remember that the i-th bit output is used as the clock for the (i+1)-th bit). count A0 A1 A2 A3 transition time due to clock-to-output times So, the FF outputs do not change at the same time due to the ripple effect in the clock inputs. We would like FF outputs to change simultaneously. This is why we prefer to design synchronous counters. ECE124 igital Circuits and Systems Page 27

28 Synchronous counters ifferent from ripple counters in that (the same) clock pulses are applied to the clock inputs of all flip-flops simultaneously. Flip-flop outputs then change simultaneously. ECE124 igital Circuits and Systems Page 28

29 Example: Synchronous Binary Up Counter Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count. Observation: A 0 is always toggling, A 1 toggles if A 0 is 1, A 2 toggles if A 0, A 1 are 1, A 3 toggles if A 0, A 1, A 2 are 1 Observations motivate the use of TFF ECE124 igital Circuits and Systems Page 29

30 Example: Synchronous Binary Up Counter Synchronous 4-bit binary up counter with enable using TFF: enable T A0 T A1 T A2 T A3 clock clear next stage ECE124 igital Circuits and Systems Page 30

31 Example: Synchronous Binary own Counter Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count. Observation: A 0 is always toggling, A 1 toggles if A 0 is 0 A 2 toggles if A 0, A 1 are 0, A 3 toggles if A 0, A 1, A 2 are 0 Observations motivate the use of TFF ECE124 igital Circuits and Systems Page 31

32 Example: Synchronous Binary own Counter Synchronous 4-bit binary down counter with enable using TFF: down T A0 T A1 T A2 T A3 clock clear next stage ECE124 igital Circuits and Systems Page 32

33 Example: Synchronous Binary Up/own Counter Can combine the up and down counter to get an up/down counter (re-use previously built circuits!) Trick is getting correct input to the FF in order to perform correct operation. Consider the following control inputs which determine circuit behaviour: ECE124 igital Circuits and Systems Page 33

34 Example: Synchronous Binary Up/own Counter Have both logic for up count and down count; up has priority (it disables down). ECE124 igital Circuits and Systems Page 34

35 Example: Synchronous Binary Up/own Counter With Parallel Load Often useful to have a counter that we can load with a starting count. This requires adding another control line (load) and data inputs: ECE124 igital Circuits and Systems Page 35

36 Example: Synchronous Binary Up/own Counter With Parallel Load load up down L U I0 T A0 I1 T A1 I2 T A2 I3 T A3 clock clear ECE124 igital Circuits and Systems Page 36

37 Comments All of the previous counters could have been built using FF or JKFF. esigning counters that perform multiple operations involves: Making sure that the correct inputs get to the FF inputs in order to perform the specific function; and The logic feeding the FF input will cause the FF output to change appropriately. If the control signals and operations have priority, we need to make sure that the control signal priority disables the operation due to other control lines (e.g., parallel load turns off up/down count signals. ECE124 igital Circuits and Systems Page 37

38 Symbols We might have different symbols to represent counters: E.g., I0 I1 I2 I3 CL UP A0 A1 A2 A3 ECE124 igital Circuits and Systems Page 38

39 Modulo counters Sometimes we don t want to count through the entire sequence of binary numbers. E.g., we might want to count 0, 1,,2,, 10 and repeat. (This is effectively a modulo- 10 counter). We could design such a counter using synchronous circuit design principles, but we could also attempt something a bit trickier We can use additional circuitry to detect our maximum count number and use a parallel load to restart the counting. ECE124 igital Circuits and Systems Page 39

40 Modulo counter build from a binary counter building block E.g., design a counter that counts 0, 1,,2,, 10 and repeats. CLK I0 A0 I1 A1 I2 A2 I3 A3 CL UP LOA ECE124 igital Circuits and Systems Page 40

41 Some Other Types of Counters: ing counters An n-bit counter in which only one output is high at any given time. E.g., Can illustrate with a timing diagram for 4-bits: CLK A0 A1 A2 A3 Outputs like this useful to generate timing signals that indicate an order of operation in another circuit block. ECE124 igital Circuits and Systems Page 41

42 Some Other Types of Counters: ing counters Can make an n-bit ring counter with a shift register. E.g., 4-bit ring counter: A0 A1 A2 A3 S clear clk To generate n non-overlapping timing signals, we need a shift register with n flip-flops. ECE124 igital Circuits and Systems Page 42

43 Some Other Types of Counters: ing counters Can also use a combination of a counter and a decoder. E.g., 4-bit ring counter with 2-bit counter and decoder. 1 CL A0 A1 x y 0 1 A0 A1 CLK 1 COUNT 2 3 A2 A3 2-bit counter 2-to-4 decoder ECE124 igital Circuits and Systems Page 43

44 Some Other Types of Counters: Switch-tail ring counters Consider the following 4-bit circuit: A0 A1 A2 A3 clear clk esembles a 4-bit ring counter, but complement of MSB fed back to LSB. ECE124 igital Circuits and Systems Page 44

45 Some Other Types of Counters: Switch-tail ring counters Count pattern can be determined: So, with n bits we get a count pattern of 2 n output states. ECE124 igital Circuits and Systems Page 45

46 Some Other Types of Counters: Johnson counters We can add additional detection circuitry in order to generate the disjoint timing signals like a ring counter. This results in a Johnson Counter. With a Johnson Counter, we can get 2 n non-overlapping timing signals using n flip-flops and some extra 2-input AN gates. ECE124 igital Circuits and Systems Page 46

47 Closing emarks Synchronous counters are nice because the counter outputs all change at the same time (according to the clock). We have only talked about some types of counters; e.g., Binary up/down counters; modulo counters. In general, counters are simply an example of a clocked sequential circuit. We can design any type of counter (e.g., any sequence of values we want) once we learn about clocked sequential circuit design (coming up in the course). E.g., we will see how to design a counter that counts 0, 3, 5, 4, 1, and repeats (if we wanted to). ECE124 igital Circuits and Systems Page 47

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

More information

Module 3: Floyd, Digital Fundamental

Module 3: Floyd, Digital Fundamental Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

More information

Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS

Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS Introduction : Logic circuit is divided into two types. 1. Combinational Logic Circuit 2. Sequential Logic Circuit Definition : 1. Combinational

More information

Counters & Shift Registers Chapter 8 of R.P Jain

Counters & Shift Registers Chapter 8 of R.P Jain Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without

More information

Digital Logic Design Sequential circuits

Digital Logic Design Sequential circuits Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register

More information

Basic bistable element. Chapter 6. Latches vs. flip-flops. Flip-flops

Basic bistable element. Chapter 6. Latches vs. flip-flops. Flip-flops Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. Flip-Flops and Simple Flip-Flop Applications.. Huang, 24 igital Logic esign

More information

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse. DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting

More information

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

More information

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters: Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary

More information

Counters and Decoders

Counters and Decoders Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

More information

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users

More information

Sequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay

Sequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit

More information

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops Sequential Circuits: Latches & Flip-Flops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc

More information

Karnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.

Karnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g. Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0

More information

Chapter 8. Sequential Circuits for Registers and Counters

Chapter 8. Sequential Circuits for Registers and Counters Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters T-FF Basic Counting element State

More information

Counters are sequential circuits which "count" through a specific state sequence.

Counters are sequential circuits which count through a specific state sequence. Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:

More information

Sequential Logic. SR Latch

Sequential Logic. SR Latch n 2/24/3 Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the

More information

3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.

3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted. 3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory

More information

Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

More information

CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS

CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop

More information

Synchronous Sequential Logic. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University

Synchronous Sequential Logic. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University Synchronous Sequential Logic Logic and Digital System Design - S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs

More information

Asynchronous counters, except for the first block, work independently from a system clock.

Asynchronous counters, except for the first block, work independently from a system clock. Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flip-flops, they can be asynchronous or synchronous and they can

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013 DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,

More information

Lecture 9: Flip-flops

Lecture 9: Flip-flops Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 9: Flip-flops Professor Peter Cheung Department of EEE, Imperial

More information

Contents COUNTER. Unit III- Counters

Contents COUNTER. Unit III- Counters COUNTER Contents COUNTER...1 Frequency Division...2 Divide-by-2 Counter... 3 Toggle Flip-Flop...3 Frequency Division using Toggle Flip-flops...5 Truth Table for a 3-bit Asynchronous Up Counter...6 Modulo

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store

More information

Figure 2.1(a) Bistable element circuit.

Figure 2.1(a) Bistable element circuit. 3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),

More information

Memory Elements. Combinational logic cannot remember

Memory Elements. Combinational logic cannot remember Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence

More information

Registers, Counters, and Clock

Registers, Counters, and Clock Registers, Counters, and Clock Z. Jerry Shi Computer Science and Engineering University of Connecticut Thank John Wakerly for providing his slides and figures. Multibit registers 74x175 (4 bits) 8-bit

More information

CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

More information

Shift registers. 1.0 Introduction

Shift registers. 1.0 Introduction Shift registers 1.0 Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from

More information

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

More information

In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current

In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current Module 12 In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current inputs. The following topics will be on sequential

More information

Chapter 14 Sequential logic, Latches and Flip-Flops

Chapter 14 Sequential logic, Latches and Flip-Flops Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 2 Sequential logic circuit, Flip Flop and Latch Introduction Ch14L2--"Digital Principles and Design", Raj Kamal, Pearson Education, 2006

More information

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012 Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

More information

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and

More information

Unit 3 Combinational MOS Logic Circuits

Unit 3 Combinational MOS Logic Circuits Unit 3 ombinational MOS Logic ircuits LATH Latch It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input

More information

An astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator can be used as a pulse generator.

An astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator can be used as a pulse generator. Concepts In sequential logic, the outputs depend not only on the inputs, but also on the preceding input values... it has memory. Memory can be implemented in 2 ways: Positive feedback or regeneration

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) (Most) Lecture material derived from R. Katz, Contemporary Logic esign, Addison Wesley Publishing Company, Reading, MA, 993. Some material

More information

Chapter 5. Flip-Flops, Registers, and Counters

Chapter 5. Flip-Flops, Registers, and Counters Chapter 5 Flip-Flops, Registers, and Counters Sensor Reset Set Memory element On Off Alarm Figure 5.1. Control of an alarm system. A B Figure 5.2. A simple memory element. Reset Set Figure 5.3. A memory

More information

Chapter 14 Sequential logic, Latches and Flip-Flops

Chapter 14 Sequential logic, Latches and Flip-Flops Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 6 - Flip Flop and -Latch Ch14L6-"igital Principles and esign", Raj Kamal, Pearson Education, 2006 2 - Flip-Flop + ve edge triggered Output

More information

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012 Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

CHAPTER 12 REGISTERS AND COUNTERS

CHAPTER 12 REGISTERS AND COUNTERS CHAPTER 12 REGISTERS AND COUNTERS This chapter in the book includes: Objectives Study Guide 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other

More information

ECE 301 Digital Electronics

ECE 301 Digital Electronics ECE 301 Digital Electronics Latches and Flip-Flops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and

More information

Asynchronous Counters. Asynchronous Counters

Asynchronous Counters. Asynchronous Counters Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter

More information

Flip-Flops, Registers, Counters, and a Simple Processor

Flip-Flops, Registers, Counters, and a Simple Processor June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

More information

BINARY CODED DECIMAL: B.C.D.

BINARY CODED DECIMAL: B.C.D. BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 Digital Logic Flip-Flops, egisters and Counters: Latches Dr. D. J. Jackson Lecture 24- torage elements Previously, we have considered combinational circuits where the output values depend only on

More information

Module-3 SEQUENTIAL LOGIC CIRCUITS

Module-3 SEQUENTIAL LOGIC CIRCUITS Module-3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.

More information

Unit 4 Session - 15 Flip-Flops

Unit 4 Session - 15 Flip-Flops Objectives Unit 4 Session - 15 Flip-Flops Usage of D flip-flop IC Show the truth table for the edge-triggered D flip-flop and edge-triggered JK flip-flop Discuss some of the timing problems related to

More information

Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See P&H 2.4 (signed), 2.5, 2.6, C.6, and Appendix C.

Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See P&H 2.4 (signed), 2.5, 2.6, C.6, and Appendix C. Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H 2.4 (signed), 2.5, 2.6, C.6, and Appendix C.6 Goals for today Binary (Arithmetic) Operations One-bit and four-bit

More information

CSE140: Components and Design Techniques for Digital Systems

CSE140: Components and Design Techniques for Digital Systems CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic

More information

CSE 271 Introduction to Digital Systems Supplementary Reading Some Basic Memory Elements

CSE 271 Introduction to Digital Systems Supplementary Reading Some Basic Memory Elements CE 27 Introduction to igital ystems upplementary eading ome Basic Memory Elements In this supplementary reading, we will show some some basic memory elements. In particular, we will pay attention to their

More information

ASYNCHRONOUS COUNTERS

ASYNCHRONOUS COUNTERS LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

More information

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count

More information

Lecture 22: Sequential Circuits. Sequential Circuits. Characteristic Table, SR Latch. S-R Latch (Clocked) Latches:

Lecture 22: Sequential Circuits. Sequential Circuits. Characteristic Table, SR Latch. S-R Latch (Clocked) Latches: Lecture 22: Sequential Circuits Latches: SR D JK Flip-Flops Memory Sequential Circuits In sequential circuits, new state depends on not only the input, but also on the previous state. Devices like registers

More information

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified

More information

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.

More information

Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here

Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here Sequential Logic Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here " E.g., 35 cents vending = cents + cents + cents +

More information

CHAPTER TEN. 10.1 New Truth Table Symbols. 10.1.1 Edges/Transitions. Memory Cells

CHAPTER TEN. 10.1 New Truth Table Symbols. 10.1.1 Edges/Transitions. Memory Cells CHAPTER TEN Memory Cells The previous chapters presented the concepts and tools behind processing binary data. This is only half of the battle though. For example, a logic circuit uses inputs to calculate

More information

Chapter 5 Bistable memory devices. Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Chapter 5 Bistable memory devices. Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Chapter 5 Bistable memory devices Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Digital circuits Combinational Sequential Logic gates Decoders, MUXes, Adders,

More information

Lecture 8: Flip-flops

Lecture 8: Flip-flops Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 8: Flip-flops Professor Peter Cheung Department of EEE, Imperial

More information

Sequential Logic Design Principles.Latches and Flip-Flops

Sequential Logic Design Principles.Latches and Flip-Flops Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch

More information

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

More information

Sequential Circuits: Latches and Flip-Flops

Sequential Circuits: Latches and Flip-Flops Sequential Circuits: Latches and Flip-Flops Sequential circuits Output depends on current input and past sequence of input(s) How can we tell if the input is current or from the past? A clock pulse can

More information

Part IA Engineering. Contents of Handout 2. Digital Circuits & Information Processing. Handout 2. Sequential Logic

Part IA Engineering. Contents of Handout 2. Digital Circuits & Information Processing. Handout 2. Sequential Logic Part IA Engineering Contents of Handout 2 Digital Circuits & Information Processing Handout 2 Sequential Logic ichard Prager Tim Flack anuary 29 Section A Section B Section C Section D Section E Binary

More information

Sequential Logic Design

Sequential Logic Design Lab #4 Sequential Logic Design Objective: To study the behavior and applications of flip flops and basic sequential circuits including shift registers and counters. Preparation: Read the following experiment.

More information

ECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo

ECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo ECE 223 Digital Circuits and Systems Synchronous Logic M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo Sequential Circuits Combinational circuits Output = f (present inputs)

More information

Master/Slave Flip Flops

Master/Slave Flip Flops Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave

More information

Design of Digital Systems II Sequential Logic Design Principles (1)

Design of Digital Systems II Sequential Logic Design Principles (1) Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic

More information

Topic Notes: Sequential Circuits

Topic Notes: Sequential Circuits Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 opic Notes: Sequential Circuits We have seen many examples of what we can do with combinational logic taking a set of

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

DIGITAL SYSTEM DESIGN LAB

DIGITAL SYSTEM DESIGN LAB EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC

More information

Flip-Flops. Outline: 2. Timing noise

Flip-Flops. Outline: 2. Timing noise Outline: 2. Timing noise Flip-Flops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. Flip-Flop memory RS-latch example D and JK flip-flops Flip-flops

More information

Latches and Flip-Flops characterestics & Clock generator circuits

Latches and Flip-Flops characterestics & Clock generator circuits Experiment # 7 Latches and Flip-Flops characterestics & Clock generator circuits OBJECTIVES 1. To be familiarized with D and JK flip-flop ICs and their characteristic tables. 2. Understanding the principles

More information

Sequential Logic: Clocks, Registers, etc.

Sequential Logic: Clocks, Registers, etc. ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design

More information

Construct a truth table for this circuit. Write Boolean expressions for X and Q.

Construct a truth table for this circuit. Write Boolean expressions for X and Q. A olution X Construct a truth table for this circuit. X X Write Boolean expressions for X and. X = (+)'; = (+X)' = ' X' = ' (+) Let = =. Then = (+) = 3 The previous circuit is called an Latch and is usually

More information

Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay

More information

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements

More information

Digital Electronics. 5.0 Sequential Logic. Module 5

Digital Electronics. 5.0 Sequential Logic.  Module 5 Module 5 www.learnabout-electronics.org Digital Electronics 5.0 Sequential Logic What you ll learn in Module 5 Section 5.0 Introduction to Sequential Logic Circuits. Section 5.1 Clock Circuits. RC Clock

More information

DEPARTMENT OF INFORMATION TECHNLOGY

DEPARTMENT OF INFORMATION TECHNLOGY DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops ESD I Lecture 3.b Sequential Circuits: Latches & Flip-Flops 1 Outline Memory elements Latch SR latch D latch Flip-Flop SR flip-flop D flip-flop JK flip-flop T flip-flop 2 Introduction A sequential circuit

More information

Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle.

More information

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential

More information

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous

More information

Set-Reset (SR) Latch

Set-Reset (SR) Latch et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0-? 0-? Indeterminate cross-coupled Nand gates

More information

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative D-Latch S-R Latch

More information

Figure 3. Ball and hill analogy for metastable behavior. S' R' Q Q next Q next ' 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 0 (a)

Figure 3. Ball and hill analogy for metastable behavior. S' R' Q Q next Q next ' 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 0 (a) Chapter 5 Latches and Flip-Flops Page 1 of 17 5. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The

More information

EKT 121/4 ELEKTRONIK DIGIT 1

EKT 121/4 ELEKTRONIK DIGIT 1 EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - Shift Registers - Basic Shift Register Functions Consist of an arrangement of flip-flops. Important in

More information

Registers & Counters

Registers & Counters Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC6 74HC/HCT/HCU/HCMOS Logic Package Information The IC6 74HC/HCT/HCU/HCMOS

More information

1. Realization of gates using Universal gates

1. Realization of gates using Universal gates 1. Realization of gates using Universal gates Aim: To realize all logic gates using NAND and NOR gates. Apparatus: S. No Description of Item Quantity 1. IC 7400 01 2. IC 7402 01 3. Digital Trainer Kit

More information

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation

More information

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

More information