BINARY CODED DECIMAL: B.C.D.


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1 BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS. *** MOST COMMON CODE CODE INDICATES THE WEIGHT OF EACH BIT E.G. 934 = FOR EACH DIGIT A BINARY [NORMAL] CODE IS ALLOCATED. OHER REPRESENTATION FORMS ARE AND EXCESS3 Ovidiu Ghita Page 77
2 BINARY EXCESS NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED 7 NOT USED 1110 NOT USED 8 NOT USED 1111 NOT USED 9 NOT USED WE WILL USE BCD DECIMAL NUMBERS > 9 MAY BE OBTAINED WHEN ADDING TWO DECIMAL DIGITS (RANGE: 018) I.E ONLY 0o9 HAVE THE CORRECT BCD CODE. WE NEED TO CORRECT THE OTHERS Ovidiu Ghita Page 78
3 DECIMAL UNCORECTED CORRECTED BCD SUM C 3 S 3 S 2 S 1 S 0 BCD SUM C N S 3 S 2 S 1 S o9 ONLY LEGAL CODES E.G. 19 = 1 9 = = THUS, FOR SUMS BETWEEN 10 o 18 MUST SUBTRACT 10 AND PRODUCE A CARRY SUBTRACT 10 = >> ADD 2 s COMPLEMENT = 0110 Ovidiu Ghita Page 79
4 4BIT BCD ADDER TO ADD TWO DIGITS FOR SUMS >9 WE NEED TO ADD 2 s COMPLEMENT of TO THE UNCORRECTED RESULT (S 3 S 2 S 1 S 0) CORRECTION IS ALSO NEEDED WHEN A CARRY OUT (C 3) IS GENERATED [NUMBERS 16 o 18] >>>> A DECODER IS REUIRED TO DETECT WHEN CARRY OUT (C N ) TO THE NEXT STAGE IS NEEDED KMAP FOR C N S 1S 0 S 0 0 3S >>> C N = C 3 + S 3S 2 +S 3S Ovidiu Ghita Page 80
5 TO IMPLEMENT A 4_BIT BCD ADDER WE NEDD TWO 4BIT FULL ADDERS, ONE TO ADD TWO 4BIT BCD NUMBERS AND THE OTHER FULL ADDER TO ADD 2 s COMPLEMENT OF TO THE RESULT IF C N = 1 ALSO WE NEED 2 AND GATES AND ONE OR GATE TO GENERATE C N B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 C 3 ' C 4 BIT ADDER OUTS ' 3 S ' 2 S ' 1 S ' C N1 FROM NEXT LOWER DIGIT C N= 0 FOR L.S. DIGIT C N TO NEXT HIGHER DIGIT 4 BIT ADDER 0 S 3 S 2 S 1 S 0 ADD 0110 WHEN C N =1 ADD 0000 WHEN C N =0 Ovidiu Ghita Page 81
6 BCD SUBTRACTION 9 s COMPLEMENT THE 9 s COMPLEMENT OF A DECIMAL NUMBER IS FOUND BY SUBTRACTING EACH DIGIT IN THE NUMBER FROM 9 DECIMAL 9 s COMPLEMENT DIGIT E.G. 9 s COMPLEMENT of 28 = = 71 9 s COMPLEMENT of 562 = = 437 SUBTRACTION OF A SMALLER DECIMAL NUMBER FROM A LARGER ONE CAN BE DONE BY ADDING THE 9 s COMPLEMENT OF THE SMALLER NUMBER TO THE LARGER NUMBER AND THEN ADDING THE CARRY TO THE RESULT (END AROUND CARRY). Ovidiu Ghita Page 82
7 WHEN SUBTRACTING A LARGER NUMBER FROM A SMALLER ONE THERE IS NO CARRY AND THE RESULT IS IN 9 s COMPLEMENT FORM AND NEGTIVE. EXAMPLES: (a) s COMP. OF 3 5 (1) 4 +1 END AROUND CARRY 5 (b) s COMP. OF 3 33 (1) END AROUND CARRY 33 (c) s COMP. OF o 13 NO CARRY >>> NEGATIVE RESULT = 13 Ovidiu Ghita Page 83
8 BCD SUBTRACTION RECALL FOR DECIMAL SUBTRACTION: A B = A + [9 s COMPLEMENT OF B] SIMILARLY FOR BCD RULES: (a) ADD 9 s COMP. OF B TO A (b) IF RESULT > 9, CORRECT BY ADDING 0110 (c) IF MOST SIGNIFICANT CARRY IS PRODUCED [i.e. =1] THEN THE RESULT IS POSITIVE AND THE END ARROUND CARRY MUST BE ADDED. (d) IF MOST SIGNIFICANT CARRY IS 0 [i.e. NO CARRY] THEN THE RESULT IS NEGATIVE AND WE GET THE 9 s COMP. OF THE RESULT Ovidiu Ghita Page 84
9 E.G. 8 3 = 8 + [9 s COMP. OF 3] = m INVALID (>9) 0110 m CORRECTION (1) m END AROUND CARRY 0101 = 5 (b) 3 8 = NO CARRY >>> NEGATIVE 9 s COMP. OF 0100 = 0101 = 5 (c) >>> 87 + [9 s COMP OF 39] INVALID 0110 (1) = 4 8 Ovidiu Ghita Page 85
10 (d) >>> 18 + [27] o NO CARRY NEGATIVE (1) 0101 CORRECTION 4 5 = 54 OUTPUT IS A NEGATIVE NUMBER >> THE RESULT IS IN 9 s COMP. FORM (e) >>> 65 + [87] (1) 0100 (1) INVALID CORRECTION END AROUND CARRY 5 3 Ovidiu Ghita Page 86
11 A 7 A 4 B 7 B 4 A 3 A 0 B 3 B 0 9 s COMP 9 s COMP BCD ADDER BCD ADDER C 0 C i C 0 C i TRUE/ 9 s COMP 0 TRUE 1 COMP. TRUE/ 9 s COMP SIGN: 0 POSITIVE 1 NEGATIVE BCD RESULT Ovidiu Ghita Page 87
12 9 s COMPLEMENT 9 s COMPLEMENT OF A NUMBER = 9 NUMBER BUT SUBTRACTORS ARE NOT WIDELY AVAILABLE >>> WE GENERATE THE 9 s COMPLEMENT BY ADDING 1010 TO THE INVERTED NUMBER BCD DIGIT DIGIT DIGIT = 9 s COMP C 3 C 2 C 1 C WE IGNORE THE CARRY OUT Ovidiu Ghita Page 88
13 EXERCISE: DESIGN A 9 s COMPLEMENT GENERATOR FOR A BCD DIGIT: B 3 B 2 B 1 B 0 IGNORE C OUT 4BIT ADDER C i 0 C 3 C 2 C 1 C 0 Ovidiu Ghita Page 89
14 OCTAL & HEXADECIMAL NUMBERS TWO MORE NUMBER SYSTEMS OCTAL >>> BASE 8 E.G. 3 8 HEXADECIMAL >>> BASE 16 E.G THE OCTAL NUMBER SYSTEM IS COMPOSED OF 8 DIGITS: 0, 1, 2, 3, 4, 5, 6, 7 TO COUNT ABOVE 7, WE BEGIN ANOTHER COLUMN AND START OVER: 10, 11, 12, 13, 14, 15, 16, 17, 20, 21, >>> COUNTING IN OCTAL IS SAME AS COUNTING IN DECIMAL EXCEPT ANY NUMBERS WITH 8 OR 9 WHICH ARE OMITTED. Ovidiu Ghita Page 90
15 THE HEXADECIMAL SYSTEM IS COMPOSED OF 16 DIGITS AND CHARACTERS. EACH HEXADECIMAL CHARACTER REPRESENTS a 4BIT BINARY NUMBER DECIMAL OCTAL HEXADECIMAL A B C D E F Ovidiu Ghita Page 91
16 DECIMAL >>> OCTAL DIVIDE BY 8, GET REMAINDERS AND READ UP : 8 15 : : READ UP >>> = Ovidiu Ghita Page 92
17 (b) :8 12 : : READ UP >>> = OCTAL >>> DECIMAL MULTIPLY BY SUCCESIVE POWERS OF = 1 x x x 8 0 = = NOTE: WE BEGIN WITH RIGHTMOST POWER OF 8 AS 8 0 DECIMAL >>> HEXADECIMAL DIVIDE BY 16, GET REMAINDERS AND READ UP NOTE: REMAINDER = 13 >>> USE CHARACTER D Ovidiu Ghita Page 93
18 E.G : 16 7 : 16 (11) B 0 7 >>> = 7B 16 HEXADECIMAL >>> DECIMAL MULTIPLY BY SUCCESIVE POWERS OF 16 NOTE: WE CONVERT A CHARACTER TO ITS DECIMAL VALUE BEFORE WE MULTIPLY E.G. 6A 16 = 6 x A x 16 0 = 6 x x 16 0 = = Ovidiu Ghita Page 94
19 SEUENTIAL LOGIC UNTIL NOW WE HAVE DEALT WITH COMBINATIONAL LOGIC WHERE THE OUTPUT DEPENDED ON THE PRESENT COMBINATION OF INPUTS IN SEUENTIAL LOGIC THE OUTPUT DEPENDS ON THE PAST INPUTS AS WELL AS PRESENT INPUTS E.G. MEMORY DEVICES USED TO REMEMBER PAST VALUES OF INPUTS FLIPFLOPS DIGITAL MEMORIES, COUNTERS AND SHIFT REGISTERS ARE BASED ON THE FLIPFLOP. THIS IS A DEVICE THAT CAN STORE 2 STATES 0 OR 1 Ovidiu Ghita Page 95
20 RS FLIPFLOP THE BASIC RS [RESET SET] FLIPFLOP CONSISTS OF 2 NOR GATES WITH THE OUTPUTS CROSSCOUPLED TO THE INPUTS R S R S 0 0 NO CHANGE NOT ALLOWED SET RESET START WITH A KNOWN STATE R = 0, S = 1 >>> = 1 SET R = 1, S = 0 >>> = 0 RESET Ovidiu Ghita Page 96
21 WHEN R=S=0, AND REMAIN AS THEY WHERE BEFORE THE INPUT WAS CHANGED R=S=1 IS NOT ALLOWED AS IT CAUSES ==0 >>> THEY HAVE TO BE OPOSITE TO EACH OTHER APPLICATION: MEMORY CELL R S N N N+1 N N = PREVIOUS STAGE (PAST) N+1 = PRESENT STAGE THE CIRCUIT IS SAID TO BE BISTABLE >>> IT CAN ASSUME TWO STABLE STATES. Ovidiu Ghita Page 97
22 RS FLIPFLOP USING NAND GATES ** TWO CROSSCOUPLED NAND GATES S R S R 0 0 NOT ALLOWED NO CHANGE SET RESET ACTIVE LOW RS THE RS FLIPFLOP CAN BE USED TO ELLIMINATE CONTACT BOUNCES IN SWITCHES. Ovidiu Ghita Page 98
23 ELECTRICAL CONTACTS OFTEN PROVIDE INPUT SIGNALS TO LOGIC SYSTEMS >>> THESE CONTACTS MAY BE A SOURCE OF NOISE DUE TO THEIR MECHANICAL PROPERTIES. +5V 2 +V 1 Oscillations due to contact bounce +5V 2 S S 1 R R 1>2 2>1 SWITCH MOVES FROM 1 TO 2 CHANGES FROM 0 TO 1 AS SOON AS THE FIRST CONTACT IS MADE (EVEN IF THE SWITCH BOUNCES STAYS AT 1) WHEN THE SWITCH MOVES FROM 2 TO 1 CHANGES FROM 1 TO 0 AS SOON AS THE FIRST CONTACT IS MADE. Ovidiu Ghita Page 99
24 SYNCHRONOUS [CLOCKED] RS FLIPFLOP WE OTEN NEED TO SET OR RESET A FLIPFLOP UNDER THE CONTROL OF A CLOCK PULSE S n S' R n R' REMEMBER: S = R = 1 NO OUTPUT CHANGE WHEN CLOCK APPLIED S N n S N R N n+1 n+1 R N FF n 0 0 n n NOT ALLOWED n = TIME BEFORE THE CLOCK PULSE n+1 = TIME AFTER THE CLOCK PULSE Ovidiu Ghita Page 100
25 HERE THE FLIPFLOP IS SET OR RESET UNDER THE CONTROL OF THE CLOCK PULSE n n+1 CLOCK PULSE WHEN IS AT 0 NO CHANGE IN OUTPUTS IRRESPECTIVE OF THE STATE OF THE INPUTS (S,R). D FLIPFLOP D [DELAY] FLIPFLOP IS A SIMPLE EXTENSION OF THE CLOCKED RS FLIPFLOP WITH THE D INPUT CONNECTED TO THE SET INPUT AND D CONNECTED TO THE RESET INPUT. Ovidiu Ghita Page 101
26 D S' R' D D FF n n D n+1 n D=1 >>> SET D=0 >> RESET ACTS AS 1BIT DTORAGE ELEMENT INPUT TRANSFERRED TO OUTPUT >>>> CALLED A LATCH. Ovidiu Ghita Page 102
27 JK FLIPFLOP JK FLIPFLOP ELIMINATES NON DEFINED (NOT ALLOWED) STATE THAT OCCURRED IN THE RS FLIPFLOP (R=S=1). MOST VERSATILE AND WIDELY USED. n J K n NO CHANGE RESET SET TOGGLE NO CHANGE RESET SET TOGGLE WHEN CLOCK ACTIVE Ovidiu Ghita Page 103
28 J A (S) K B (R) DIFFERS TO RS BY USING ADDITIONAL FEEDBACK WHEN CLOCK ACTIVE J K FF J K n n NO CHANGE RESET SET 1 1 n TOGGLE SAME AS RS FLIPFLOP EXCEPT WHEN J=K=1. Ovidiu Ghita Page 104
29 E.G. =0 [=1] >>> RESET THEN CLOCK GOES FROM 0 o 1 >>> Ao0 >>> =1 Bo1 >>> =1 >>> SET MASTER SLAVE JK FLIPFLOP PROBLEM WITH JK FLIPFLOP >>> OUTPUTS MAY CHANGE IF THE DATA INPUTS [J,K,,] CHANGE WHILE THE CLOCK IS HIGH >>> WE NEED TO MAKE SURE THAT AND DO NOT ASSUME THEIR NEW VALUES UNTIL AFTER THE TRAILING EDGE ON THE CLOCK PULSE i.e. WHEN PULSE o 0 RISING OR LEADING EDGE FALLING OR TRAILING EDGE Ovidiu Ghita Page 105
30 WE DO THIS BY USING A MASTERSLAVE [MS] FLIPFLOP >>> DIVIDE THE FLIPFLOP INTO MASTER + SLAVE FLIPFLOP. MASTER SLAVE J K m m WHEN THE CLOCK PULSE IS HIGH THE JK INPUTS ARE APPLIED TO THE MASTER FLIPFLOP AND THE SLAVE INPUT IS NOT AFFECTED (=0) WHEN THE CLOCK PULSE FALLS TO ZERO, THE DATA FROM THE MASTER IS APPLIED TO THE SLAVE INPUTS AND THE OUTPUTS AND GET THEIR NEW VALUES. ANOTHER RESTRICTION: THE INPUTS J AND K DO NOT CHANGE WHILE =1 Ovidiu Ghita Page 106
31 A RS MASTER SLAVE FLIPFLOP MAY ALSO BE CONSTRUCTEDIN A SIMILAR FASHION, THE ONLY DIFFERENCE IS THAT WHEN THE TWO INPUTS J=K=1 THE OUTPUT CHANGES IS STATE ON RECEIPT OF THE CLOCK PULSE i.e. THE FLIPFLOP TOGGLES. J K n n UNCAHGED RESET SET 1 1 n TOGGLE DIFFERENT APPROACH: WE WILL NOW LOOK AT THE JK FLIP FLOP IN A SLIGHTLY DIFFERENT WAY IF n = 0 AND J = 0 >>> n+1 = 0 REGARDLESS OF K IF n = 0 AND J = 1 >>> n+1 = 1 REGARDLESS OF K Ovidiu Ghita Page 107
32 IF n = 1 AND K = 0 >>> n+1 = 1 REGARDLESS OF J IF n = 1 AND K = 1 >>> n+1 = 0 REGARDLESS OF J J K n n+1 n+1 0 X X X X X o DEFINES A DON T CARE TERM o USEFUL IN DESIGNING LOGIC SYSTEMS WITH JK FLIP FLOPS THE MASTERSLAVE FLIPFLOPS ARE SYNCRONOUS DEVICES >>> THE OUTPUT CHANGES STATE AT A SPECIFIED POINT ON A CLOCK INPUT. Ovidiu Ghita Page 108
33 JK FLIPFLOP WITH ASYNCHRONOUS SET AND RESET INPUTS SEPARATE SET AND RESET INPUTS MAY BE ADDED TO THE JK FLIP FLOP. THESE SET & RESET INPUTS [S,R] OVERRIDE THE J,K INPUTS AND ARE ASYNCHRONOUS [i.e. OVERRIDE THE CLOCK ALSO]. NOTE: WHEN S = R = 1 >>> WE HAVE NORMAL FLIPFLOP OPERATION S J K R Ovidiu Ghita Page 109
34 TRUTH TABLE: S R J K n X X NOT ALLOWED 0 1 X X X X n NORMAL OPERATION n Ovidiu Ghita Page 110
35 FLIPFLOP APPLICATIONS REGISTERS: GROUPS OF FLIPFLOPS ARRANGED TO PROVIDE DATA STORAGE FOR SEVERAL DATA BITS. 1. DATA REGISTER A JK FLIPFLOP CAN BE USED AS A 1BIT EMORY [D FLIPFLOP] BY APPLYING THE BIT TO BE STORED [D] TO J AND ITS INVERSE [D] TO K. AN n BIT BINARY WORD CAN BE STORED BY n SUCH FLIPFLOPS >>>> CALLED A nbit REGISTER. PARALLEL DATA STORAGE, i.e. SEVERAL BITS ON PARALLEL LINES STORED SIMULTANEOUSLY. Ovidiu Ghita Page 111
36 D3 D2 D D 1 0 K J K J K J K J 3 2 DATA BITS (D 3 D 0 ) ARE STORED ON THE RECEIPT OF THE CLOCK PULSE SHIFT REGISTER SERIAL DATA TRANSFER [i.e. ONE BIT AT A TIME], A WORD OF NBITS READ INTO NFLIPFLOP SHIFT REGISTER THE FIRST FLIPFLOP HOLDS THE WORD S MSB AND IS CONNECTED AS A D FLIPFLOP. Ovidiu Ghita Page 112
37 E.G. 4 BIT SHIFT REGISTER SERIAL INPUT J K J J J K K K 3 = MSB REMEMBER: J K n OUTPUT FOLLOWS JINPUT WHEN J = K >>> SHIFT OCCURS WHEN CLOCK APPLIED. Ovidiu Ghita Page 113
38 SHIFT REGISTER OPERATION: LSB OF SERIAL DATA IS APPLIED TO THE SERIAL INPUT [J 3 ]. THE CLOCK PULSE IS APPLIED AND LSB GOES INTO 3 [= J 2 ]. THE NEXT LSB IS THEN APPLIED TO J 3 AND AFTER A CLOCK PULSE IT IS STORED IN 3, WHILE AT THE SAME TIME THE LSB IS SHIFTED INTO 2. AFTER 4 CLOCK PULSES THE SERIAL DATA IS STORED IN THE SHIFT REGISTER. E.G. STORE THE WORD: SERIAL INPUT ASSUME THE STORED WORD IS INITIALLY Ovidiu Ghita Page 114
39 3. SHIFT REGISTERS WITH PARALLEL INPUTS [PARALLEL TO SERIAL CONVERTER] LOAD BITS IN PARALLEL FORM AND SFIFT THEM IN SERIAL FORM. DATA IS LOADED BY APPLYING SIGNALS TO ASYNCHRONOUS SET/RESET INPUTS OF THE JK FLIP FLOP. PARALLEL LOAD D 3 D 3 D 2 D 2 D 1 D 1 D0 D 0 SERIAL INPUT J K S J S J S J S R K R K R K R SERIAL OUTPUT PARALLEL DATA IS LOADED BY APPLYING A CLOCK PULSE TO PARALLEL LOAD SIGNAL. Ovidiu Ghita Page 115
40 WHEN PARALLEL LOAD IS LOW THE CIRCUIT OPERATES AS A NORMAL SHIFT REGISTER [S = R = 1] WHEN PARALLEL LOAD IS HIGH THEN PARALLEL DATA IS LOADED ASYNCRONOUSLY [INDEPENDENT OF THE CLOCK] AND SHIFTED OUT SYNCHRONOUSLY. 4. RIGHTLEFT SHIFT REGISTER SHIFT REGISTERS CAN ALSO BE USED TO TRANSFER DATA FROM RIGHT TO LEFT, SFIFT LEFT, BY CONNECTING THE OUTPUT OF A FLIPFLOP BACK TO THE INPUT OF THE FLIPFLOP ON ITS LEFT A SHIFT FROM LEFT TO RIGHT, SHIFT RIGHT, CAN BE CARRIED OUT DURING NORMAL OPERATION OF THE SHIFT REGISTER. Ovidiu Ghita Page 116
41 A SHIFT RIGHT AND SHIFT LEFT REGISTER CAN BE COMBINED BY SUITABLE GATING AND CONTROL SIGNALS. NOTE R/L >>> R/L = 0 >>> SHIFT RIGHT R/L = 1 >>> SHIFT LEFT R/L SERIAL IN RIGHT SERIAL IN LEFT J K J J SERIAL OUT LEFT K SERIAL OUT RIGHT K Ovidiu Ghita Page 117
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