L4: Sequential Building Blocks (Flipflops, Latches and Registers)


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1 L4: Sequential Building Blocks (Flipflops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified Microelectronics Corporation istinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington epartment of Computer Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic esign. 2nd ed. PrenticeHall/Pearson Education, 25. J. Rabaey, A. Chandrakasan, B. Nikolic. igital Integrated Circuits: A esign Perspective. Prentice Hall/Pearson, 23. L4: 6. Spring 26 Introductory igital Systems Laboratory
2 Combinational Logic Review in in Combinational Circuit in in in N in M Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct value L4: 6. Spring 26 Introductory igital Systems Laboratory 2
3 A Sequential System Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state Memory element Sequential circuits have memory (i.e., remember the past) The current state is held in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of events L4: 6. Spring 26 Introductory igital Systems Laboratory 3
4 A Simple Example Adding N inputs (N Adders) in in in2 in N Using a sequential (serial) approach reset in Current_Sum clk L4: 6. Spring 26 Introductory igital Systems Laboratory 4
5 Implementing State: Bistability V o =V i2 V o2 =V i V i2 = V o Point C is Metastable C V o V i2 V i2 =V o V i A V o2 δ V i = V o2 V i2 = V o A Points A and B are stable (represent & ) C B V i =V o2 δ B V i = V o2 L4: 6. Spring 26 Introductory igital Systems Laboratory 5
6 NORbased SetReset (SR) Flipflop S S R S R SR =, SR =, SR = SR = SR = SR = SR = SR = SR = R Forbidden State SR = SR = Reset Hold Set Reset Set R S?? Flipflop refers to a bistable element (edgetriggered registers are also called flipflops) this circuit is not clocked and outputs change asynchronously with the inputs L4: 6. Spring 26 Introductory igital Systems Laboratory 6
7 Making a Clocked Memory Element: Positive Latch S R G clk R and S clock sample hold sample hold A Positive Latch: Passes input to output when is high and holds state when clock is low (i.e., ignores input ) A Latch is levelsensitive: invert clock for a negative latch L4: 6. Spring 26 Introductory igital Systems Laboratory 7 hold
8 Multiplexor Based Positive & Negative Latch 2: multiplexor Positive Latch Negative Latch in in out SEL Out = sel * in + sel * in "data" clk "load" clk "remember" "stored value" L4: 6. Spring 26 Introductory igital Systems Laboratory 8
9 74HC75 (Positive Latch) LE 2 CP L 3 2 CP Operating Modes Inputs Outputs LE nn n n n LE 34 L2 CP L3 3 3 ata Enabled ata Latched H L L H H H H L L X q q CP L4 4 8 Figures by MIT OpenCourseWare. L4: 6. Spring 26 Introductory igital Systems Laboratory 9
10 Building an EdgeTriggered Register Negative latch Positive latch M G G Master Slave M M MasterSlave Register Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch View pair as one basic unit masterslave flipflop twice as much logic Image by MIT OpenCourseWare. L4: 6. Spring 26 Introductory igital Systems Laboratory
11 Latches vs. EdgeTriggered Register Edge triggered device sample inputs on the event edge 7474 Transparent latches sample inputs as long as the clock is asserted Positive edgetriggered register Timing iagram: 7475 C Levelsensitive latch Bubble here for negative edge triggered register Behavior the same unless input changes while the clock is high L4: 6. Spring 26 Introductory igital Systems Laboratory
12 Important Timing Parameters Clock Clock: Periodic Event, causes state of memory element to change Input T su T h There is is a timing "window" around the clocking event during which the input must remain stable and unchanged in in order to to be be recognized memory element can be updated on the: rising edge, falling edge, high level, low level Setup Time (T su ) Minimum time before the clocking event by which the input must be stable Hold Time (T h ) Minimum time after the clocking event during which the input must remain stable Propagation elay (T cq for an edgetriggered register and T dq for a latch) elay overhead of the memory element L4: 6. Spring 26 Introductory igital Systems Laboratory 2
13 The JK J K FlipFlop Flop J K S R J K + + J K \ Eliminate the forbidden state of the SR Flipflop Use output feedback to guarantee that R and S are never both one L4: 6. Spring 26 Introductory igital Systems Laboratory 3
14 JK K MasterSlave Register Sample inputs while clock high Sample inputs while clock low J P S S K R P R 's Set Reset Catch T oggle J K Correct Toggle Operation J φ K P \ P \ Master outputs Slave outputs Is there a problem with this circuit? L4: 6. Spring 26 Introductory igital Systems Laboratory 4
15 Pulse Based EdgeTriggered JK J K Register Input X φ Input φ Output X t plh Schematic Output J φ K S R J φ K JK Register Logic Symbol JK Register Schematic L4: 6. Spring 26 Introductory igital Systems Laboratory 5
16 PulseTriggered Registers Ways to design an edgetriggered sequential cell: MasterSlave Latches PulseBased Register ata L L2 ata Latch Short pulse around clock edge Pulse registers are widely used in highperformance microprocessor chips (Sun Microsystems, AM, Intel, etc.) The can have a negative setup time! L4: 6. Spring 26 Introductory igital Systems Laboratory 7
17 FlipFlop Flop vs. Toggle FlipFlop Flop FlipFlop N T T (Toggle) FlipFlop T N N N L4: 6. Spring 26 Introductory igital Systems Laboratory 6
18 Realizing ifferent Types of Memory Elements Characteristic Equations : JK: T: + = + = J + K + = T + T E.g., J=K=, then + = J=, K=, then + = J=, K=, then + = J=, K=, then + = Implementing One FF in Terms of Another J C K K J C implemented with JK JK implemented with L4: 6. Spring 26 Introductory igital Systems Laboratory 7
19 esign Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? + J X X K X X T Implementing FF with a JK FF: ) Start with Kmap of + = ƒ(, ) 2) Create Kmaps for J and K with same inputs (, ) 3) Fill in Kmaps with appropriate values for J and K to cause the same state changes as in the original Kmap E.g., = =, + = then J =, K = X X X X X + = J = K = L4: 6. Spring 26 Introductory igital Systems Laboratory 8
20 esign Procedure (cont.) Implementing JK FF with a FF: ) KMap of + = F(J, K, ) 2,3) Revised Kmap using 's excitation table its the same! that is why design procedure with FF is simple! JK J K + = = J + K Resulting equation is the combinational logic input to to cause same behavior as JK FF. Of course it is identical to the characteristic equation for a JK FF. L4: 6. Spring 26 Introductory igital Systems Laboratory 9
21 System Timing Parameters In Combinational Logic Register Timing Parameters T cq : worst case rising edge clock to q delay T cq, cd : contamination or minimum delay from clock to q T su : setup time T h : hold time Logic Timing Parameters T logic : worst case delay through the combinational logic network T logic,cd : contamination or minimum delay through logic network L4: 6. Spring 26 Introductory igital Systems Laboratory 2
22 System Timing (I): Minimum Period In Combinational Logic CLout T h T h IN T su T cq T su T cq FF T cq,cd T logic T cq,cd CLout T l,cd T su2 T > T cq + T logic + T su L4: 6. Spring 26 Introductory igital Systems Laboratory 2
23 System Timing (II): Minimum elay In Combinational Logic CLout IN FF CLout T su T h T cq,cd T h T l,cd T cq,cd + T logic,cd > T hold L4: 6. Spring 26 Introductory igital Systems Laboratory 22
24 ShiftRegister Typical parameters for Positive edgetriggered Register Tsu 2ns Th 5ns Tsu 2ns Th 5ns Tw 25ns Tplh 25ns 3ns Tphl 4ns 25ns all measurements are made from the clocking event that is, the rising edge of the clock Shiftregister IN OUT IN L4: 6. Spring 26 Introductory igital Systems Laboratory 23
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