Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop."

Transcription

1 Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage and limitation of an S-R flip-flop. recognise the arrangement of NAND gates used to form a clocked S-R flip-flop. complete a timing diagram for an S-R flip-flop. recognise the arrangement of NAND gates used to form a D-type flip-flop. describe the advantages of a D-type flip-flop. complete a timing diagram for a D-type flip-flop.

2 COMBINATIONAL LOGIC SYSTEMS Up to this point we have been investigating combinational logic systems. The output state of a combinational logic system can be worked out from its circuit diagram, provided we know the present state of its inputs. EXAMPLE A B C Fig. Combinational logic system You should be able to work out that = for the input settings shown. The Boolean equation representing the function of the system is: = A.B + C i.e. Output is if A = AND B =, OR if C =. SEUENTIAL LOGIC SYSTEMS The output state of a sequential logic circuit can only be worked out if we know the present, and previous, state of its inputs i.e. if we know the sequence of events that have occurred at its inputs The basic element in any sequential logic system is a flip-flop circuit. In this Chapter we shall be considering 2 types of flip-flops. the S-R flip-flop, and the D-type Flip-flop You will discover how feedback between outputs and inputs is used to give them a form of memory. 2

3 PROPERTIES OF FLIP-FLOP CIRCUITS Flip-flops have two outputs which are usually labelled and. The bar indicates that is the inverse of i.e. = when =. = = Inputs Inputs = = { { SET state RESET state Fig. 2 The stable states of a flip-flop Flip-flops can settle in any one of two stable states and are often referred to as bistable circuits. The two stable states are illustrated in Fig 2. Note that: in the SET state, = and =. in the RESET state, = and =. Let us now consider the three types in some detail. 3

4 A. THE S-R FLIP-FLOP Fig 3 shows how two NAND gates can be arranged to form an S-R flip-flop. +5V R S Note that: V Fig. 3 An S-R Flip-flop inputs are normally held at logic level by the pull-up resistors. Closing a switch pulls an input down to logic level. the bars on the S and R indicate that they are activated by operating switches which pull them down to logic level. feedback is applied by connecting the outputs back to inputs. the output is on the same gate as the S input. Fig 4 illustrates how an S-R flip-flop can settle in any one of two stable states when the power supply is switchedon, with neither S nor R switches pressed. Note how the same input conditions can produce different output states. The pull-up resistors and switches have not been included on the diagram. S S R R Set state Reset state 4 Fig. 4

5 Fig 5 illustrates a switching sequence for an S-R flip-flop. S S R R S R (a) (b) S R (c) (d) Fig. 5 In Fig 7.5a, the flip-flop is in its RESET state with both inputs at logic level. If the SET input is pulled down to logic level (Fig 7.5b), its output changes to logic level and the flip-flop settles in its SET state. REMINDER: The output of a NAND gate is logic level if one, or both, of its inputs are at logic level. When the SET input returns to logic level (Fig 5c) the flip-flop remains in its SET state. It remembers the event that took place at the SET input and latches in this state. Any further changes at the SET input will have no effect upon the output. The flip-flop can be reset by momentarily pulling its RESET input down to logic level (Fig 5d). 5

6 The following truth table illustrates the switching action for the sequence. S INPUT R INPUT OUTPUT OUTPUT (Fig 5a) SET action. (Fig 5b) No change at output. (Fig 5c) RESET action. (Fig 5d) No change at output. Fig. 6 Truth table for S-R flipflop DISADVANTAGE AND LIMITATION OF AN S-R FLIP-FLOP If both inputs are pulled down to logic level, both outputs will be at logic level. This state should not be allowed to occur in flip-flops. The output state of an S-R flip-flop changes whenever the inputs are activated. In most electronic systems, several changes have to be synchronised to occur at the same time. Flip-flops used in such systems should be fitted with a clock or strobe input. 6

7 DISADVANTAGE OF A CLOCKED S-R FLIP-FLOP If both inputs are held at logic level, both outputs can be at logic level C. THE D-TYPE FLIP FLOP The disadvantages of the flip-flops previously considered can be overcome by using a D type flip-flop, the main inputs, as shown in Fig 7. The D-type flip-flop has one data input and a clock input. Changing the D-input to logic level only produces no change at the output. D Clock Fig 7 The logic level at the D-input is transferred to the output at the instant when the clock signal is changing from logic level to logic level. Any changes at the D-input after the clock has reached logic level will be ignored. In the exercise you will be investigating D-type flip-flops contained in a 7474 IC package. You will discover that these flip-flops are rising edge triggered 7

8 Clock D-Input Fig. 8 Timing diagram for an edge-triggered flip-flop Fig 9 shows the logic symbol commonly used for a D-type flip-flop. D S CP R Fig. 9 Logic symbol for D-type flip-flop S and R can be used to set and reset the flip-flop. The circles indicate that they are active low Signals on S and R take effect immediately. They do not need a clock pulse to be present. The clock input is labelled CP (Clock Point). 8

9 APPLICATIONS. LATCHING If the D-input is connected to logic level, the flip-flop will latch in its set state when it receives a clock pulse. +5V D CLOCK R Fig. The clock pulse could be provided by an input transducer such as a light sensing unit. 2. DIVIDING BY 2 ( T type flip flop) If the D-input is connected to the output, as shown in Fig, the frequency of the signal at the output will be half of that applied at the clock input, provided the T input is high, if the T input is low the output will not toggle. This action will be investigated further in Activity 3. D T input Fig. 9

10 Exercise Objectives Having completed this Exercise you should be able to: construct and investigate an S-R flip flop made up from two NAND gates. construct and investigate a D-type flip flop made up from four NAND gates and an inverter. investigate a 7474 Dual D-type IC package. COMPONENTS REUIRED 7474 IC PACKAGE (Dual D-type)

11 ACTIVITY : We shall start this Exercise by investigating an S-R Flip-flop circuit. a. Set up the following arrangement: Use Press Switches on the Experiment Card Master Board to provide the falling edges at the SET (S) and RESET (R) inputs. Use the Logic Monitors to monitor the outputs and. S INPUT R INPUT b. Try to complete the following truth table before switching on the Power Supplies. S INPUT R INPUT c. Switch on the Power Supplies. If the indicator comes ON, reset the system by momentarily pressing the R INPUT switch.

12 d. Work through the sequence of input settings to check your predictions. INFORMATION A similar type of flip-flop can be formed using NOR gates. In this case the inputs are active high and the output is taken from the gate which has the RESET input connected to it. 2

13 DESIGN PROBLEM A system is required which latches on a flashing LED when it gets dark. It should be possible to manually reset the system during daylight hours. (a) (b) (c) Draw a logic circuit diagram showing a suitable circuit. Provide a brief explanation of how it works. Set up the system and evaluate its performance. 3

14 ACTIVITY 2: Activity 2 requires an experiment card which allows different chips to be investigated. 2a. Insert a 7474 Dual D-type IC package into one of the sockets on Experiment Card 9.3. Pin should be at the bottom left hand corner. Vcc R D2 D 2 CP 2 S D R D D CP S D GND 2b. Set up the following arrangement with the Board Clock set to its slowest speed. Pin numbers have been included to help you with the construction. Note that the Set and Reset inputs have been connected to +5V. Power supply connections on pins 7 and 4 are not shown on the diagram. Use Logic Monitors to monitor Clock Input and output. +5V 4 Press 2 5 To Logic switch D S Monitor Board clock 3 CP R 6 +5V 2c. By operating the press switch connected to the D-input and observing the Logic Monitor LEDs, decide when the D-input state is transferred to the output. 4

15 ACTIVITY 3: 3a. Set up the following D-type flip-flop arrangement. The D-input has been connected to the output. Press or slide switch Logic +5V Monitor D S 3 R 6 Press or slide switch 3b. Switch on the Power Supplies. If the Logic Monitor LED is on, momentarily operate the reset Press Switch B. 3c. Operate the clock input Press Switch A eight times i.e. apply 8 pulses at the clock input, and count the number of output pulses provided at the output. Complete the following diagram to illustrate the action of the arrangement when a steady train of pulses is applied at the clock input. Clock

16 3d. Extend the system, as shown below, using the second D-type flipflop in the 7474 IC package. (2 ) (2 ) A +5V +5V D S D S 3 R 6 R 8 B 3 3e. Operate the clock pulse Press Switch A eight times and count the number of output pulses obtained from the output. Complete the following diagram to illustrate the action of the arrangement when a steady train of pulses is applied at the clock input. Clock f. Disconnect the link from pin 3 to Switch A then connect pin 3 to the Board Clock output. 6

17 3g. Use a CRO to enable you to set a Clock input to provide pulses of frequency Hz. ms 3h. Use your CRO to measure the period of the signal provided at the output. Period of output = Frequency at output= 3i. Use your CRO to measure the period of the signal provided at the output. Period of output = Frequency at output= 3j. Set the Clock to its slowest possible speed. Observe the Logic Monitor. You should be able to see that the arrangement forms a binary counter, providing the binary counting sequence from zero to 3. } 2 3 } } }

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

Lecture-3 MEMORY: Development of Memory:

Lecture-3 MEMORY: Development of Memory: Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,

More information

Digital Fundamentals

Digital Fundamentals igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage

More information

Flip-Flops, Registers, Counters, and a Simple Processor

Flip-Flops, Registers, Counters, and a Simple Processor June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

More information

Lecture 7: Clocking of VLSI Systems

Lecture 7: Clocking of VLSI Systems Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 Two-Phase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10 - Clocking Note: The analysis

More information

1.1 The 7493 consists of 4 flip-flops with J-K inputs unconnected. In a TTL chip, unconnected inputs

1.1 The 7493 consists of 4 flip-flops with J-K inputs unconnected. In a TTL chip, unconnected inputs CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-246 Digital Logic Lab EXPERIMENT 1 COUNTERS AND WAVEFORMS Text: Mano, Digital Design, 3rd & 4th Editions, Sec.

More information

Development of a Simple Sound Activated Burglar Alarm System

Development of a Simple Sound Activated Burglar Alarm System [ Leonardo Journal of Sciences ISSN 1583-0233 Issue 9, July-December 2006 p. 97-102 Development of a Simple Sound Activated Burglar Alarm System Department of Electrical and Computer Engineering, Federal

More information

Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems

Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH

More information

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7-segment decoder driver incorporating input latches and constant current output circuits

More information

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit - FSM A Sequential circuit contains: Storage

More information

IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)

IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584-640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines

More information

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates

More information

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit A Sequential circuit contains: Storage elements:

More information

Lecture 10: Sequential Circuits

Lecture 10: Sequential Circuits Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing

More information

VCE Physics and VCE Systems Engineering: Table of electronic symbols

VCE Physics and VCE Systems Engineering: Table of electronic symbols VCE Physics and VCE Systems Engineering: Table of electronic symbols In response to requests from teachers the VCAA has produced a table of commonly used electronic symbols. Practicing teachers have provided

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS

More information

Sequential Circuit Design

Sequential Circuit Design Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines

More information

Lecture 11: Sequential Circuit Design

Lecture 11: Sequential Circuit Design Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current

More information

DATA SHEETS DE COMPONENTES DA FAMÍLIA LÓGICA TTL GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS DESCRIÇÃO

DATA SHEETS DE COMPONENTES DA FAMÍLIA LÓGICA TTL GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS DESCRIÇÃO GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS Hex Invertes 74LS04 Quadruple 2 Inputs Gates 74LS00 Triple 3 Inputs Gates 74LS10 Dual 4 Inputs Gates 74LS20 8 Inputs Gates 74LS30 13 Inputs Gates

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

CpE358/CS381. Switching Theory and Logical Design. Class 4

CpE358/CS381. Switching Theory and Logical Design. Class 4 Switching Theory and Logical Design Class 4 1-122 Today Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification

More information

MODEL 5010 DUAL CHANNEL SMOKE/FIRE DETECTION MODULE

MODEL 5010 DUAL CHANNEL SMOKE/FIRE DETECTION MODULE DESCRIPTION MODEL 5010 DUAL CHANNEL SMOKE/FIRE DETECTION MODULE DESCRIPTION The SST Model 5010 Two Channel Smoke/Fire Detection Module provides two independent detection input channels for the NOVA-5000

More information

EVAL-UFDC-1/UFDC-1M-16

EVAL-UFDC-1/UFDC-1M-16 Evaluation Board for Universal Frequency-to- Digital Converters UFDC-1 and UFDC-1M-16 EVAL-UFDC-1/UFDC-1M-16 FEATURES Full-Featured Evaluation Board for the Universal Frequency-to-Digital Converters UFDC-1

More information

Latch Timing Parameters. Flip-flop Timing Parameters. Typical Clock System. Clocking Overhead

Latch Timing Parameters. Flip-flop Timing Parameters. Typical Clock System. Clocking Overhead Clock - key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where

More information

DP8570A DP8570A Timer Clock Peripheral (TCP)

DP8570A DP8570A Timer Clock Peripheral (TCP) DP8570A DP8570A Timer Clock Peripheral (TCP) Literature Number: SNAS557 DP8570A Timer Clock Peripheral (TCP) General Description The DP8570A is intended for use in microprocessor based systems where information

More information

Programmable Single-/Dual-/Triple- Tone Gong SAE 800

Programmable Single-/Dual-/Triple- Tone Gong SAE 800 Programmable Single-/Dual-/Triple- Tone Gong Preliminary Data SAE 800 Bipolar IC Features Supply voltage range 2.8 V to 18 V Few external components (no electrolytic capacitor) 1 tone, 2 tones, 3 tones

More information

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

Active Learning in the Introduction to Digital Logic Design Laboratory Course

Active Learning in the Introduction to Digital Logic Design Laboratory Course Active Learning in the Introduction to Digital Logic Design Laboratory Course Jing Pang Department of Electrical and Electronic Engineering, Computer Engineering Program, California State University, Sacramento,

More information

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating

More information

Control/Communicator Installation Manual

Control/Communicator Installation Manual DAS NETWORX NX-8 Control/Communicator Installation Manual Page General Description... 2 Ordering Information... 2 Option Definitions... 2 Programming the LED Code Pads... 4 Programming the NX-8... 8 Types

More information

Chapter 2 Clocks and Resets

Chapter 2 Clocks and Resets Chapter 2 Clocks and Resets 2.1 Introduction The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due

More information

Simplifying Logic Circuits with Karnaugh Maps

Simplifying Logic Circuits with Karnaugh Maps Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified

More information

EE552. Advanced Logic Design and Switching Theory. Metastability. Ashirwad Bahukhandi. (Ashirwad Bahukhandi) bahukhan@usc.edu

EE552. Advanced Logic Design and Switching Theory. Metastability. Ashirwad Bahukhandi. (Ashirwad Bahukhandi) bahukhan@usc.edu EE552 Advanced Logic Design and Switching Theory Metastability by Ashirwad Bahukhandi (Ashirwad Bahukhandi) bahukhan@usc.edu This is an overview of what metastability is, ways of interpreting it, the issues

More information

Design Verification & Testing Design for Testability and Scan

Design Verification & Testing Design for Testability and Scan Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing

More information

Single 2.5V - 3.6V or 2.7V - 3.6V supply Atmel RapidS serial interface: 66MHz maximum clock frequency. SPI compatible modes 0 and 3

Single 2.5V - 3.6V or 2.7V - 3.6V supply Atmel RapidS serial interface: 66MHz maximum clock frequency. SPI compatible modes 0 and 3 32Mb, 2.5V or 2.7V Atmel ataflash ATASHEET Features Single 2.5V - 3.6V or 2.7V - 3.6V supply Atmel RapidS serial interface: 66MHz maximum clock frequency SPI compatible modes 0 and 3 User configurable

More information

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1 ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

More information

DS1821 Programmable Digital Thermostat and Thermometer

DS1821 Programmable Digital Thermostat and Thermometer ma www.maxim-ic.com FEATURES Requires no external components Unique 1-Wire interface requires only one port pin for communication Operates over a -55 C to +125 C (67 F to +257 F) temperature range Functions

More information

RETRIEVING DATA FROM THE DDC112

RETRIEVING DATA FROM THE DDC112 RETRIEVING DATA FROM THE by Jim Todsen This application bulletin explains how to retrieve data from the. It elaborates on the discussion given in the data sheet and provides additional information to allow

More information

The Programming Interface

The Programming Interface : In-System Programming Features Program any AVR MCU In-System Reprogram both data Flash and parameter EEPROM memories Eliminate sockets Simple -wire SPI programming interface Introduction In-System programming

More information

Fig 3. PLC Relay Output

Fig 3. PLC Relay Output 1. Function of a PLC PLC Basics A PLC is a microprocessor-based controller with multiple inputs and outputs. It uses a programmable memory to store instructions and carry out functions to control machines

More information

DS1621 Digital Thermometer and Thermostat

DS1621 Digital Thermometer and Thermostat Digital Thermometer and Thermostat www.dalsemi.com FEATURES Temperature measurements require no external components Measures temperatures from 55 C to +125 C in 0.5 C increments. Fahrenheit equivalent

More information

EvB 5.1 v5 User s Guide

EvB 5.1 v5 User s Guide EvB 5.1 v5 User s Guide Page 1 Contents Introduction... 4 The EvB 5.1 v5 kit... 5 Power supply...6 Programmer s connector...7 USB Port... 8 RS485 Port...9 LED's...10 Pushbuttons... 11 Potentiometers and

More information

LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING

LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING A thesis work submitted to the faculty of San Francisco State University In partial fulfillment of the requirements for

More information

GTS-4E Hardware User Manual. Version: V1.1.0 Date: 2013-12-04

GTS-4E Hardware User Manual. Version: V1.1.0 Date: 2013-12-04 GTS-4E Hardware User Manual Version: V1.1.0 Date: 2013-12-04 Confidential Material This document contains information highly confidential to Fibocom Wireless Inc. (Fibocom). Fibocom offers this information

More information

Technical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview

Technical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview Technical Note TN-29-06: NAND Flash Controller on Spartan-3 Overview Micron NAND Flash Controller via Xilinx Spartan -3 FPGA Overview As mobile product capabilities continue to expand, so does the demand

More information

PCAN-MicroMod Universal I/O Module with CAN Interface. User Manual. Document version 2.1.0 (2014-01-16)

PCAN-MicroMod Universal I/O Module with CAN Interface. User Manual. Document version 2.1.0 (2014-01-16) PCAN-MicroMod Universal I/O Module with CAN Interface User Manual Document version 2.1.0 (2014-01-16) Products taken into account Product Name Part number Model PCAN-MicroMod IPEH-002080 with firmware

More information

Telecommunications Switching Systems (TC-485) PRACTICAL WORKBOOK FOR ACADEMIC SESSION 2011 TELECOMMUNICATIONS SWITCHING SYSTEMS (TC-485) FOR BE (TC)

Telecommunications Switching Systems (TC-485) PRACTICAL WORKBOOK FOR ACADEMIC SESSION 2011 TELECOMMUNICATIONS SWITCHING SYSTEMS (TC-485) FOR BE (TC) PRACTICAL WORKBOOK FOR ACADEMIC SESSION 2011 TELECOMMUNICATIONS SWITCHING SYSTEMS (TC-485) FOR BE (TC) Department of Electronic Engineering NED University of Engineering and Technology, Karachi LABORATORY

More information

Cellphone Based Device Control With Voice Acknowledgement

Cellphone Based Device Control With Voice Acknowledgement Cellphone Based Device Control With Voice Acknowledgement Avigyan Datta Gupta 1, Sayan Samanta 2, Avishek Acharjee 3 1,2 Future Institute of Engineering and Management, Kolkata-700150 3 Techno India, Kolkata-700150

More information

POWER-VOLTAGE MONITORING IC WITH WATCHDOG TIMER

POWER-VOLTAGE MONITORING IC WITH WATCHDOG TIMER FUJITSU SEMICONDUCTOR DATA SHEET DS04-27402-2E ASSP POWER-VOLTAGE MONITORING IC WITH WATCHDOG TIMER MB3793-42/30 DESCRIPTION The MB3793 is an integrated circuit to monitor power voltage; it incorporates

More information

DS1621 Digital Thermometer and Thermostat

DS1621 Digital Thermometer and Thermostat www.maxim-ic.com FEATURES Temperature measurements require no external components Measures temperatures from -55 C to +125 C in 0.5 C increments. Fahrenheit equivalent is -67 F to 257 F in 0.9 F increments

More information

Supply voltage Supervisor TL77xx Series. Author: Eilhard Haseloff

Supply voltage Supervisor TL77xx Series. Author: Eilhard Haseloff Supply voltage Supervisor TL77xx Series Author: Eilhard Haseloff Literature Number: SLVAE04 March 1997 i IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to

More information

Develop a Dallas 1-Wire Master Using the Z8F1680 Series of MCUs

Develop a Dallas 1-Wire Master Using the Z8F1680 Series of MCUs Develop a Dallas 1-Wire Master Using the Z8F1680 Series of MCUs AN033101-0412 Abstract This describes how to interface the Dallas 1-Wire bus with Zilog s Z8F1680 Series of MCUs as master devices. The Z8F0880,

More information

Installation Manual for D1110 DigiCom2

Installation Manual for D1110 DigiCom2 Installation Manual for D1110 DigiCom2 Dycon Ltd Tel: +44 (0)1443 471 060 Fax: +44 (0)1443 479 374 Cwm Cynon Business Park Mountain Ash CF45 4ER - UK www.dyconsecurity.com sales@dyconsecurity.com TABLE

More information

Multilevel Sequential Logic Circuit Design

Multilevel Sequential Logic Circuit Design International Journal of Electronics and Electrical Engineering Vol., No. 4, December, 4 Multilevel Sequential Logic Circuit Design vni Morgül FSM Vakıf University, iomedical Eng. Dept, Istanbul, Turkey

More information

TONE/PULSE DIALER WITH REDIAL

TONE/PULSE DIALER WITH REDIAL INTRODUCTION The KS58006 is DTMF/PULSE switchable dialer with a 32-digit redial which can be done using a slide switch. All necessary dual-tone frequencies are derived from a 3.579545 MHz T crystal or

More information

SWITCH-MODE POWER SUPPLY CONTROLLER PULSE OUTPUT DC OUTPUT GROUND EXTERNAL FUNCTION SIMULATION ZERO CROSSING INPUT CONTROL EXTERNAL FUNCTION

SWITCH-MODE POWER SUPPLY CONTROLLER PULSE OUTPUT DC OUTPUT GROUND EXTERNAL FUNCTION SIMULATION ZERO CROSSING INPUT CONTROL EXTERNAL FUNCTION SWITCH-MODE POWER SUPPLY CONTROLLER. LOW START-UP CURRENT. DIRECT CONTROL OF SWITCHING TRAN- SISTOR. COLLECTOR CURRENT PROPORTIONAL TO BASE-CURRENT INPUT REERSE-GOING LINEAR OERLOAD CHARACTERISTIC CURE

More information

Accurate Measurement of the Mains Electricity Frequency

Accurate Measurement of the Mains Electricity Frequency Accurate Measurement of the Mains Electricity Frequency Dogan Ibrahim Near East University, Faculty of Engineering, Lefkosa, TRNC dogan@neu.edu.tr Abstract The frequency of the mains electricity supply

More information

Tutorials Drawing a 555 timer circuit

Tutorials Drawing a 555 timer circuit Step 1 of 10: Introduction This tutorial shows you how to make an electronic circuit using Livewire and PCB Wizard 3. You should follow this tutorial to learn the basic skills you will need to use Livewire

More information

Writing Assignment #2 due Today (5:00pm) - Post on your CSC101 webpage - Ask if you have questions! Lab #2 Today. Quiz #1 Tomorrow (Lectures 1-7)

Writing Assignment #2 due Today (5:00pm) - Post on your CSC101 webpage - Ask if you have questions! Lab #2 Today. Quiz #1 Tomorrow (Lectures 1-7) Overview of Computer Science CSC 101 Summer 2011 Main Memory vs. Auxiliary Storage Lecture 7 July 14, 2011 Announcements Writing Assignment #2 due Today (5:00pm) - Post on your CSC101 webpage - Ask if

More information

2/4, 4/5/6 CLOCK GENERATION CHIP

2/4, 4/5/6 CLOCK GENERATION CHIP 2/4, 4/5/6 CLOCK GENERATION CHIP FEATURES 3.3V and 5V power supply option 50ps output-to-output skew 50% duty cycle outputs Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input

More information

Introduction to VLSI Programming. TU/e course 2IN30. Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.

Introduction to VLSI Programming. TU/e course 2IN30. Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat. Introduction to VLSI Programming TU/e course 2IN30 Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.Lab] Introduction to VLSI Programming Goals Create silicon (CMOS) awareness

More information

If an occupancy of room is zero, i.e. room is empty then light source will be switched off automatically

If an occupancy of room is zero, i.e. room is empty then light source will be switched off automatically EE389 Electronic Design Lab Project Report, EE Dept, IIT Bombay, Nov 2009 Fully-automated control of lighting and security system of a Room Group No: D2 Bharat Bhushan (06d04026) Sravan

More information

DMD 101 Introduction to DMD technology

DMD 101 Introduction to DMD technology TI DN 2510331 Rev A March 2009 Introduction to DMD technology This document describes basic structure and operation of the DMD array. May not be reproduced without the permission of Texas Instruments Incorporated

More information

M68EVB908QL4 Development Board for Motorola MC68HC908QL4

M68EVB908QL4 Development Board for Motorola MC68HC908QL4 M68EVB908QL4 Development Board for Motorola MC68HC908QL4! Axiom Manufacturing 2813 Industrial Lane Garland, TX 75041 Email: Sales@axman.com Web: http://www.axman.com! CONTENTS CAUTIONARY NOTES...3 TERMINOLOGY...3

More information

Watt Saver for a Cell Phone AC Adapter. Reference Design

Watt Saver for a Cell Phone AC Adapter. Reference Design Watt Saver for a Cell Phone AC Adapter Reference Design Document Number: DRM130 Rev 1, 10/2013 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1 Introduction 1.1 Overview...5

More information

ARM Thumb Microcontrollers. Application Note. Software ISO 7816 I/O Line Implementation. Features. Introduction

ARM Thumb Microcontrollers. Application Note. Software ISO 7816 I/O Line Implementation. Features. Introduction Software ISO 7816 I/O Line Implementation Features ISO 7816-3 compliant (direct convention) Byte reception and transmission with parity check Retransmission on error detection Automatic reception at the

More information

United States Patent [191

United States Patent [191 United States Patent [191 Fancy [54] REDUNDANT SIGNAL CIRCUIT [75] Inventor: Thomas A. Fancy, Westminster, Mass. [73] Assignee: General Electric Company, Schenectady, NY. [211 Appl. No.: 854,973 [22] Filed:

More information

W03 Analysis of DC Circuits. Yrd. Doç. Dr. Aytaç Gören

W03 Analysis of DC Circuits. Yrd. Doç. Dr. Aytaç Gören W03 Analysis of DC Circuits Yrd. Doç. Dr. Aytaç Gören ELK 2018 - Contents W01 Basic Concepts in Electronics W02 AC to DC Conversion W03 Analysis of DC Circuits (self and condenser) W04 Transistors and

More information

Digital Systems. Syllabus 8/18/2010 1

Digital Systems. Syllabus 8/18/2010 1 Digital Systems Syllabus 1 Course Description: This course covers the design and implementation of digital systems. Topics include: combinational and sequential digital circuits, minimization methods,

More information

Fault Modeling. Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults. Transistor faults Summary

Fault Modeling. Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults. Transistor faults Summary Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at

More information

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department

More information

GSM AUTO DIALER. Remote Monitoring & Control using your mobile phone. www.gsm-activate.co.uk

GSM AUTO DIALER. Remote Monitoring & Control using your mobile phone. www.gsm-activate.co.uk GSM AUTO DIALER Remote Monitoring & Control using your mobile phone www.gsm-activate.co.uk Product Information Our GSM Auto-Dialer is a versatile unit which can be attached to many of your electronic devices

More information

PACKAGE OUTLINE DALLAS DS2434 DS2434 GND. PR 35 PACKAGE See Mech. Drawings Section

PACKAGE OUTLINE DALLAS DS2434 DS2434 GND. PR 35 PACKAGE See Mech. Drawings Section PRELIMINARY DS2434 Battery Identification Chip FEATURES Provides unique ID number to battery packs PACKAGE OUTLINE Eliminates thermistors by sensing battery temperature on chip DALLAS DS2434 1 2 3 256

More information

TX 2C/RX 2C TOY CAR REMOTE CONTROLLER WITH FIVE FUNCTIONS

TX 2C/RX 2C TOY CAR REMOTE CONTROLLER WITH FIVE FUNCTIONS TOY CAR REMOTE CONTROLLER WITH FIVE FUNCTIONS DESCRIPTION The TX 2C/RX 2C is a pair of CMOS LSIs designed for remote controlled car applications. The TX 2C/RX 2C has five control keys for controlling the

More information

www.jameco.com 1-800-831-4242

www.jameco.com 1-800-831-4242 Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. LF411 Low Offset, Low Drift JFET Input Operational Amplifier General Description

More information

EE360: Digital Design I Course Syllabus

EE360: Digital Design I Course Syllabus : Course Syllabus Dr. Mohammad H. Awedh Fall 2008 Course Description This course introduces students to the basic concepts of digital systems, including analysis and design. Both combinational and sequential

More information

LONGLINE QSFP+ SR4. Features. Applications. Description. Page 1 of 13

LONGLINE QSFP+ SR4. Features. Applications. Description. Page 1 of 13 LONGLINE QSFP+ SR4 Features 4 channels full-duplex transceiver modules Transmission data rate up to 10.5Gbps per channel 4 channels 850nm VCSEL array 4 channels PIN photo detector array Low power consumption

More information

Introduction to CMOS VLSI Design

Introduction to CMOS VLSI Design Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, Addison-Wesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration

More information

AN10724. TDA8026ET - 5 slots smart card interface. Document information

AN10724. TDA8026ET - 5 slots smart card interface. Document information Rev. 1.0 27 September 2011 Application note Document information Info Content Keywords TDA8026, 5 slots, Smart Card Interface, Banking, EMV, Point-Of-Sale, ISO 7816-3 Abstract This application note describes

More information

ezsystem elab16m Project 1F: Alarm System (Full Project description)

ezsystem elab16m Project 1F: Alarm System (Full Project description) ezsystem elab16m Project 1F: Alarm System (Full Project description) ezsystem The aim of ezsystem is to enable Creativity and Innovation at an early age in a Problem Based Learning (PBL) approach. ezsystem

More information

KA7500C. SMPS Controller. Features. Description. Internal Block Diagram. www.fairchildsemi.com

KA7500C. SMPS Controller. Features. Description. Internal Block Diagram. www.fairchildsemi.com SMPS Controller www.fairchildsemi.com Features Internal Regulator Provides a Stable 5V Reference Supply Trimmed to ±1% Accuracy. Uncommitted Output TR for 200mA Sink or Source Current Output Control for

More information

Allows the user to protect against inadvertent write operations. Device select and address bytes are Acknowledged Data Bytes are not Acknowledged

Allows the user to protect against inadvertent write operations. Device select and address bytes are Acknowledged Data Bytes are not Acknowledged Write Protect CAT24WCxxx I 2 C Serial EEPROMs. Allows the user to protect against inadvertent write operations. WP = V CC : Write Protected Device select and address bytes are Acknowledged Data Bytes are

More information

USER GUIDE Programming Adapter Cable for Fujitsu Flash Microcontroller- F²MC-16LX/FR Family Fujitsu Microelectronics America, Inc.

USER GUIDE Programming Adapter Cable for Fujitsu Flash Microcontroller- F²MC-16LX/FR Family Fujitsu Microelectronics America, Inc. USER GUIDE Programming Adapter Cable for Fujitsu Flash Microcontroller- F²MC-16LX/FR Family Fujitsu Microelectronics America, Inc. 1 Revision History Revision # Date Comment 1.0 03.25.2001 New Document

More information

Theft preventer alarm Click here for Circuit Diagram. Power supply failure alarm Click here for Circuit Diagram.

Theft preventer alarm Click here for Circuit Diagram. Power supply failure alarm Click here for Circuit Diagram. Theft preventer alarm Click here for Circuit Diagram. This circuit utilising a 555 timer IC can be used as an alarm system to prevent the theft of your luggage, burglars breaking into your house etc. The

More information

IDS X-Series User Manual 700-398-01D Issued July 2012

IDS X-Series User Manual 700-398-01D Issued July 2012 1 2 Contents 1. Introduction to the IDS X-Series Panels... 7 2. Before Operating Your Alarm System... 7 3. Understanding the Keypad LEDs... 8 3.1 Viewing Data on an LED Keypad... 12 3.1.1 LED Status Indicators...

More information

Digital Signal Controller Based Automatic Transfer Switch

Digital Signal Controller Based Automatic Transfer Switch Digital Signal Controller Based Automatic Transfer Switch by Venkat Anant Senior Staff Applications Engineer Freescale Semiconductor, Inc. Abstract: An automatic transfer switch (ATS) enables backup generators,

More information

MANUAL FOR BREAKOUT BOARD HG06

MANUAL FOR BREAKOUT BOARD HG06 MANUAL FOR BREAKOUT BOARD HG06 INFORMATION IS SPECIFIC TO OUR PRODUCTS AND CAN CAUSE DAMAGE IF USED WITH NONE COMPATIBLE PRODUCTS SO PLEASE CHECK WITH YOUR SUPPLIER FOR COMPATIBILITY These drawings are

More information

Induced voltages and Inductance Faraday s Law

Induced voltages and Inductance Faraday s Law Induced voltages and Inductance Faraday s Law concept #1, 4, 5, 8, 13 Problem # 1, 3, 4, 5, 6, 9, 10, 13, 15, 24, 23, 25, 31, 32a, 34, 37, 41, 43, 51, 61 Last chapter we saw that a current produces a magnetic

More information

CpE358/CS381. Switching Theory and Logical Design. Class 10

CpE358/CS381. Switching Theory and Logical Design. Class 10 CpE358/CS38 Switching Theory and Logical Design Class CpE358/CS38 Summer- 24 Copyright 24-373 Today Fundamental concepts of digital systems (Mano Chapter ) Binary codes, number systems, and arithmetic

More information

Computer Engineering 290. Digital Design: I. Lecture Notes Summer 2002

Computer Engineering 290. Digital Design: I. Lecture Notes Summer 2002 Computer Engineering 290 Digital Design: I Lecture Notes Summer 2002 W.D. Little Dept. of Electrical and Computer Engineering University of Victoria 1 Preface These lecture notes complement the material

More information

SHADOWSENSE PERFORMANCE REPORT: LATENCY

SHADOWSENSE PERFORMANCE REPORT: LATENCY SHADOWSENSE PERFORMANCE REPORT: LATENCY I. DOCUMENT REVISION HISTORY Revision Date Author Comments 1.1 Now\19\2015 John La Re formatted for release 1.0 July\06\2015 Jason Tang Yuk Created the document

More information

8741A UNIVERSAL PERIPHERAL INTERFACE 8-BIT MICROCOMPUTER

8741A UNIVERSAL PERIPHERAL INTERFACE 8-BIT MICROCOMPUTER UNIVERSAL PERIPHERAL INTERFACE 8-BIT MICROCOMPUTER 8-Bit CPU plus ROM RAM I O Timer and Clock in a Single Package One 8-Bit Status and Two Data Registers for Asynchronous Slave-to- Master Interface DMA

More information

Using the Siemens S65 Display

Using the Siemens S65 Display Using the Siemens S65 Display by Christian Kranz, October 2005 ( http://www.superkranz.de/christian/s65_display/displayindex.html ) ( PDF by Benjamin Metz, 01 st November 2005 ) About the Display: Siemens

More information

Memory Module Specifications KVR667D2D4F5/4G. 4GB 512M x 72-Bit PC2-5300 CL5 ECC 240-Pin FBDIMM DESCRIPTION SPECIFICATIONS

Memory Module Specifications KVR667D2D4F5/4G. 4GB 512M x 72-Bit PC2-5300 CL5 ECC 240-Pin FBDIMM DESCRIPTION SPECIFICATIONS Memory Module Specifications KVR667DD4F5/4G 4GB 5M x 7-Bit PC-5300 CL5 ECC 40- FBDIMM DESCRIPTION This document describes s 4GB (5M x 7-bit) PC-5300 CL5 SDRAM (Synchronous DRAM) fully buffered ECC dual

More information

ID-2LA, ID-12LA, ID-20LA

ID-2LA, ID-12LA, ID-20LA 1 ID-2 Series Datasheet X1 ID-2LA, ID-12LA, ID-20LA Low Voltage Series Reader Modules Datasheet Version1.0 Date 09/01/13 2 ID-2 Series Datasheet X1 Content 1. Overview... 3 2. Pin Out for ID12-LA and ID20-LA...

More information

SSD1298. Advance Information. 240 RGB x 320 TFT LCD Controller Driver integrated Power Circuit, Gate and Source Driver with built-in RAM

SSD1298. Advance Information. 240 RGB x 320 TFT LCD Controller Driver integrated Power Circuit, Gate and Source Driver with built-in RAM SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1298 Advance Information 240 RGB x 320 TFT LCD Controller Driver integrated Power Circuit, Gate and Source Driver with built-in RAM This document contains

More information

AT&T SPIRIT. Communications System User Manual

AT&T SPIRIT. Communications System User Manual AT&T SPIRIT Communications System User Manual Table of Contents How to Use this Manual 2 Key to Symbols 4 Ringing Patterns 5 Groups (2448 System) 5 Indicator Light Patterns 5 Parts of the Telephones 6

More information

Chapter 5 :: Memory and Logic Arrays

Chapter 5 :: Memory and Logic Arrays Chapter 5 :: Memory and Logic Arrays Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 5- ROM Storage Copyright 2007 Elsevier 5- ROM Logic Data

More information

Module 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1

Module 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1 Module 2 Embedded Processors and Memory Version 2 EE IIT, Kharagpur 1 Lesson 5 Memory-I Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would Pre-Requisite

More information

Switch Actuator, 8-fold, 10 A, MDRC AT/S 8.10.1, GH Q631 0075 R0111

Switch Actuator, 8-fold, 10 A, MDRC AT/S 8.10.1, GH Q631 0075 R0111 , GH Q631 0075 R0111 The 8-fold switch actuator is a DIN rail mounted device for insertion in the distribution board. It is connected to the EIB via a bus terminal. In the event of bus voltage failure,

More information