# Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

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1 Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage and limitation of an S-R flip-flop. recognise the arrangement of NAND gates used to form a clocked S-R flip-flop. complete a timing diagram for an S-R flip-flop. recognise the arrangement of NAND gates used to form a D-type flip-flop. describe the advantages of a D-type flip-flop. complete a timing diagram for a D-type flip-flop.

2 COMBINATIONAL LOGIC SYSTEMS Up to this point we have been investigating combinational logic systems. The output state of a combinational logic system can be worked out from its circuit diagram, provided we know the present state of its inputs. EXAMPLE A B C Fig. Combinational logic system You should be able to work out that = for the input settings shown. The Boolean equation representing the function of the system is: = A.B + C i.e. Output is if A = AND B =, OR if C =. SEUENTIAL LOGIC SYSTEMS The output state of a sequential logic circuit can only be worked out if we know the present, and previous, state of its inputs i.e. if we know the sequence of events that have occurred at its inputs The basic element in any sequential logic system is a flip-flop circuit. In this Chapter we shall be considering 2 types of flip-flops. the S-R flip-flop, and the D-type Flip-flop You will discover how feedback between outputs and inputs is used to give them a form of memory. 2

3 PROPERTIES OF FLIP-FLOP CIRCUITS Flip-flops have two outputs which are usually labelled and. The bar indicates that is the inverse of i.e. = when =. = = Inputs Inputs = = { { SET state RESET state Fig. 2 The stable states of a flip-flop Flip-flops can settle in any one of two stable states and are often referred to as bistable circuits. The two stable states are illustrated in Fig 2. Note that: in the SET state, = and =. in the RESET state, = and =. Let us now consider the three types in some detail. 3

4 A. THE S-R FLIP-FLOP Fig 3 shows how two NAND gates can be arranged to form an S-R flip-flop. +5V R S Note that: V Fig. 3 An S-R Flip-flop inputs are normally held at logic level by the pull-up resistors. Closing a switch pulls an input down to logic level. the bars on the S and R indicate that they are activated by operating switches which pull them down to logic level. feedback is applied by connecting the outputs back to inputs. the output is on the same gate as the S input. Fig 4 illustrates how an S-R flip-flop can settle in any one of two stable states when the power supply is switchedon, with neither S nor R switches pressed. Note how the same input conditions can produce different output states. The pull-up resistors and switches have not been included on the diagram. S S R R Set state Reset state 4 Fig. 4

5 Fig 5 illustrates a switching sequence for an S-R flip-flop. S S R R S R (a) (b) S R (c) (d) Fig. 5 In Fig 7.5a, the flip-flop is in its RESET state with both inputs at logic level. If the SET input is pulled down to logic level (Fig 7.5b), its output changes to logic level and the flip-flop settles in its SET state. REMINDER: The output of a NAND gate is logic level if one, or both, of its inputs are at logic level. When the SET input returns to logic level (Fig 5c) the flip-flop remains in its SET state. It remembers the event that took place at the SET input and latches in this state. Any further changes at the SET input will have no effect upon the output. The flip-flop can be reset by momentarily pulling its RESET input down to logic level (Fig 5d). 5

6 The following truth table illustrates the switching action for the sequence. S INPUT R INPUT OUTPUT OUTPUT (Fig 5a) SET action. (Fig 5b) No change at output. (Fig 5c) RESET action. (Fig 5d) No change at output. Fig. 6 Truth table for S-R flipflop DISADVANTAGE AND LIMITATION OF AN S-R FLIP-FLOP If both inputs are pulled down to logic level, both outputs will be at logic level. This state should not be allowed to occur in flip-flops. The output state of an S-R flip-flop changes whenever the inputs are activated. In most electronic systems, several changes have to be synchronised to occur at the same time. Flip-flops used in such systems should be fitted with a clock or strobe input. 6

7 DISADVANTAGE OF A CLOCKED S-R FLIP-FLOP If both inputs are held at logic level, both outputs can be at logic level C. THE D-TYPE FLIP FLOP The disadvantages of the flip-flops previously considered can be overcome by using a D type flip-flop, the main inputs, as shown in Fig 7. The D-type flip-flop has one data input and a clock input. Changing the D-input to logic level only produces no change at the output. D Clock Fig 7 The logic level at the D-input is transferred to the output at the instant when the clock signal is changing from logic level to logic level. Any changes at the D-input after the clock has reached logic level will be ignored. In the exercise you will be investigating D-type flip-flops contained in a 7474 IC package. You will discover that these flip-flops are rising edge triggered 7

8 Clock D-Input Fig. 8 Timing diagram for an edge-triggered flip-flop Fig 9 shows the logic symbol commonly used for a D-type flip-flop. D S CP R Fig. 9 Logic symbol for D-type flip-flop S and R can be used to set and reset the flip-flop. The circles indicate that they are active low Signals on S and R take effect immediately. They do not need a clock pulse to be present. The clock input is labelled CP (Clock Point). 8

9 APPLICATIONS. LATCHING If the D-input is connected to logic level, the flip-flop will latch in its set state when it receives a clock pulse. +5V D CLOCK R Fig. The clock pulse could be provided by an input transducer such as a light sensing unit. 2. DIVIDING BY 2 ( T type flip flop) If the D-input is connected to the output, as shown in Fig, the frequency of the signal at the output will be half of that applied at the clock input, provided the T input is high, if the T input is low the output will not toggle. This action will be investigated further in Activity 3. D T input Fig. 9

10 Exercise Objectives Having completed this Exercise you should be able to: construct and investigate an S-R flip flop made up from two NAND gates. construct and investigate a D-type flip flop made up from four NAND gates and an inverter. investigate a 7474 Dual D-type IC package. COMPONENTS REUIRED 7474 IC PACKAGE (Dual D-type)

11 ACTIVITY : We shall start this Exercise by investigating an S-R Flip-flop circuit. a. Set up the following arrangement: Use Press Switches on the Experiment Card Master Board to provide the falling edges at the SET (S) and RESET (R) inputs. Use the Logic Monitors to monitor the outputs and. S INPUT R INPUT b. Try to complete the following truth table before switching on the Power Supplies. S INPUT R INPUT c. Switch on the Power Supplies. If the indicator comes ON, reset the system by momentarily pressing the R INPUT switch.

12 d. Work through the sequence of input settings to check your predictions. INFORMATION A similar type of flip-flop can be formed using NOR gates. In this case the inputs are active high and the output is taken from the gate which has the RESET input connected to it. 2

13 DESIGN PROBLEM A system is required which latches on a flashing LED when it gets dark. It should be possible to manually reset the system during daylight hours. (a) (b) (c) Draw a logic circuit diagram showing a suitable circuit. Provide a brief explanation of how it works. Set up the system and evaluate its performance. 3

14 ACTIVITY 2: Activity 2 requires an experiment card which allows different chips to be investigated. 2a. Insert a 7474 Dual D-type IC package into one of the sockets on Experiment Card 9.3. Pin should be at the bottom left hand corner. Vcc R D2 D 2 CP 2 S D R D D CP S D GND 2b. Set up the following arrangement with the Board Clock set to its slowest speed. Pin numbers have been included to help you with the construction. Note that the Set and Reset inputs have been connected to +5V. Power supply connections on pins 7 and 4 are not shown on the diagram. Use Logic Monitors to monitor Clock Input and output. +5V 4 Press 2 5 To Logic switch D S Monitor Board clock 3 CP R 6 +5V 2c. By operating the press switch connected to the D-input and observing the Logic Monitor LEDs, decide when the D-input state is transferred to the output. 4

15 ACTIVITY 3: 3a. Set up the following D-type flip-flop arrangement. The D-input has been connected to the output. Press or slide switch Logic +5V Monitor D S 3 R 6 Press or slide switch 3b. Switch on the Power Supplies. If the Logic Monitor LED is on, momentarily operate the reset Press Switch B. 3c. Operate the clock input Press Switch A eight times i.e. apply 8 pulses at the clock input, and count the number of output pulses provided at the output. Complete the following diagram to illustrate the action of the arrangement when a steady train of pulses is applied at the clock input. Clock

16 3d. Extend the system, as shown below, using the second D-type flipflop in the 7474 IC package. (2 ) (2 ) A +5V +5V D S D S 3 R 6 R 8 B 3 3e. Operate the clock pulse Press Switch A eight times and count the number of output pulses obtained from the output. Complete the following diagram to illustrate the action of the arrangement when a steady train of pulses is applied at the clock input. Clock f. Disconnect the link from pin 3 to Switch A then connect pin 3 to the Board Clock output. 6

17 3g. Use a CRO to enable you to set a Clock input to provide pulses of frequency Hz. ms 3h. Use your CRO to measure the period of the signal provided at the output. Period of output = Frequency at output= 3i. Use your CRO to measure the period of the signal provided at the output. Period of output = Frequency at output= 3j. Set the Clock to its slowest possible speed. Observe the Logic Monitor. You should be able to see that the arrangement forms a binary counter, providing the binary counting sequence from zero to 3. } 2 3 } } }

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