Chapter 5. Sequential Logic


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1 Chapter 5 Sequential Logic
2 Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends on present inputs and present states (pre. inputs) (inputs, current state) (outputs, next state) synchronous: the transition happens at discrete instants of time asynchronous: at any instant of time
3 Sequential Circuits (2/2) A sequential circuit is specified by a time sequence of inputs, outputs and internal states Sequential circuits must be able to remember the past history Flipflops: most commonly used memory devices A function of  present inputs &  present state of memory elements (the past sequence of inputs)
4 Clock Use clock pulses generated by a clock generator Fig. 5.2 Synchronous clocked sequential circuit
5 Types of Sequential Circuits depending on the timing of their signals Synchronous ( ) sequential circuits Storage elements are affected at discrete time instants Use clock pulses in the inputs of storage elements Asynchronous ( ) sequential circuits Storage elements are affected at any time instant
6 Synchronous Sequential Circuits (/2) Synchronous Use clock pulses in the inputs of storage elements Storage elements are affected only with the arrival of each pulse The storage elements used in the clocked sequential circuits are called flipflops
7 Synchronous Sequential Circuits (2/2) Synchronous sequential circuits a masterclock generator to generate a periodic train of clock pulses the clock pulses are distributed throughout the system clocked sequential circuits (most popular) no instability problems the memory elements: flipflops binary cells capable of storing one bit of information two outputs: one for the normal value and one for the complement value maintain a binary state indefinitely until directed by an input signal to switch states
8 Latches (/3) The most basic types of flipflops operate with signal levels latch All FFs are constructed from the latches introduced here A FF can maintain a binary state indefinitely until directed by an input signal to switch states Two NOR gates Set, Reset
9 Latches (2/3) IF R= S= IF R= S= Step : red number Step 2: yellow number Step 3: green number Step 4: black number
10 Latches (3/3) S R P=Q Q more complicated types can be built upon it an asynchronous sequential circuit (S,R)= (,): no operation * * // a stable state in the previous state // change to another stable state Set // remain in the previous state // change to another stable state Reset // remain in the previous state // oscillate (unpredictable) if next SR= the condition should be avoided (S,R)=(,): reset (Q=, the clear state) (S,R)=(,): set (Q=, the set state) (S,R)=(,): indeterminate state (Q=Q'=) consider (S,R) = (,) (,) Q
11 SR Latch with NAND gates SR latch with NAND gates reset set S R latch (c) Graphic symbol
12 SR Latch with Control Input S_ /S' The complement output of the previous R S latch. / R_ /R' En=, no change En=, enable En En=, no change En=, enable En (c) Graphic symbol (c) Graphic symbol
13 D Latch (Transparent Latch) S_ /D' / R_ /D eliminate the undesirable conditions of the indeterminate state in the RS flipflop D: data gated Dlatch D Q when En=; no change when En= En D QQ level triggered (levelsensitive)
14 FlipFlops A trigger The state of a latch or flipflop is switched by a change of the control input Level triggered latches Edge triggered flipflops Level triggered Edge triggered Edge triggered
15 Problem of Latch If leveltriggered flipflops are used the feedback path may cause instability problem (since the time interval of logic is too long) multiple transitions might happen during logic level Edgetriggered flipflops the state transition happens only at the edge eliminate the multipletransition problem
16 EdgeTriggered D FlipFlop Two designs to solve the problem of latch: a. Masterslave D flipflop b. Edgetrigger D flipflop Masterslave D flipflop two separate flipflops a master latch (positivelevel triggered) a slave latch (negativelevel triggered)
17 Masterslave D flipflop (/2) Two D latches and one inverter The circuit samples D input and changes its output Q only at the negativeedge of CLK isolate the output of FF from being affected while its input is changing CLK=, enabled CLK=, disabled CLK=, disabled CLK=, enabled
18 Masterslave D flipflop (2/2) CP = : (S,R) (Y,Y'); (Q,Q') holds CP = : (Y,Y') holds; (Y,Y') (Q,Q') (S,R) could not affect (Q,Q') directly the state changes coincide with the negativeedge transition of CP
19 EdgeTriggered FlipFlops (/2) the state changes during a clockpulse transition A Dtype positiveedgetriggered flipflop Three SR latches
20 EdgeTriggered FlipFlops (2/2) (S,R) = (,): Q = (S,R) = (,): Q = (S,R) = (,): no operation (S,R) = (,): should be avoided # #2 (new) (old) If Clk= S= and R= no operation. Output Q remains in the present state. #3 #4 If Clk= and D= R= Reset. Output Q is. Then, if D changes to, R remains at and Q is. Then, Clk= S=, R= no operation (Q=) Then, if Clk= and D= S= Set. Output Q is. (see the blue dotline flow) Then, if D changes to, S remains at and Q=;
21 PositiveEdgeTriggered FlipFlops Summary Clk=: (S,R) = (,), no state change Clk= : state change once Clk=: state holds eliminate the feedback problems in sequential circuits All flipflops must make their transition at the same time
22 FlipFlops A trigger The state of a latch or flipflop is switched by a change of the control input Level triggered latches Edge triggered flipflops Level triggered Edge triggered Edge triggered
23 Setup Time and Hold Time The setup time D input must be maintained at a constant value prior to the application of the positive Clk pulse = the propagation delay through gates 4 and data to the internal latches The hold time D input must not changes after the application of the positive Clk pulse = the propagation delay of gate 3 (try to understand) clock to the internal latch
24 Timing Diagram 2.8 ns setup time hold time.4 ns
25 PositiveEdge vs. NegativeEdge The edgetriggered D flipflops The most economical and efficient The most popular flipflop Positiveedge and negativeedge
26 Latch vs. FlipFlop Level triggered Edge triggered positiveedge triggered Latch negativeedge triggered CLK D QQ CLK CLK
27 Clock Period clock period clock width rising falling edge edge Clock period (measured in micro or nanoseconds) is the time between successive transitions in the same direction Clock frequency (measured in MHz or GHz) is the reciprocal of clock period Clock width is the time interval during which clock is equal to Duty cycle is the ratio of the clock width and clock period Clock signal is active high if the changes occur at the rising edge or during the clock width. Otherwise, it is active low
28 Latch and FlipFlop rising edge falling edge Latches are levelsensitive since they respond to input changes during clock width. Latches are difficult to work with for this reason. FlipFlops respond to input changes only during the change in clock signal (the rising edge or the falling edge). They are easy to work with though more expensive than latches. Two basic styles of flipflops are available: () masterslave (2) edgetriggered
29 D flipflop + external logic JK FlipFlop (*clear=) All operations must be finished in the interval Inputs J, K disabled K enabled J enabled J, K enabled J K D Q(t+) Function Q(t) Q(t) no change reset FF to set FF to Q (t) Q (t) complement output positiveedge
30 T(Toggle) FlipFlop Characteristic Table T Q(t+) Q(t) no change Q (t) complement (a) based on JK FF (b) based on D FF D = T Q = TQ +T Q J K Q(t+) Q(t) no change reset set Q (t) complement  tie J,K together T D Q(t+) Q Q(t) no change Q Q (t) complement Complementing FF T=: a clock edge complements the output useful for designing binary counters
31 Characteristic Equations/Tables of FFs Characteristic Equations define next state Q(t+) as a function of inputs and present state algebraically Characteristic Tables define next state Q(t+) as a function of inputs and present state Q(t) in tabular form Q(t+) = JQ + K Q Q(t+) = T Q = TQ + T Q Q(t+) = D
32 Direct inputs asynchronous set and/or asynchronous reset S_ reset_ Fig. 5.4 D flipflop with asynchronous reset
33 Direct Input Preset (PRE) an asynchronous input that sets the FF direct set Clear (CLR) an asynchronous input that clears the FF direct reset Purpose Can be used to bring all FFs in a system to a known state prior to the clocked operation Asynchronous set: Set as soon as preset = Synchronous set: Set when preset= and CLK
34 D FlipFlop with Asynchronous Reset need reset active low FF triggers on the positive edge of CLK
35 Analysis of Clocked Sequential Ckts A sequential circuit (inputs, current state) (output, next state) a state transition table or state transition diagram Ax Ax +Bx Bx A 'x A+B State (transition) equation A(t+) = A(t)x(t) + B(t)x(t) B(t+) = A'(t)x(t) A compact form A(t+) = Ax + Bx B(t+) = A'x The output equation y(t) = (A(t)+B(t))x'(t) y = (A+B)x'
36 State table A(t + ) =Ax + Bx B(t + ) = A x y = Ax + Bx
37 A(t + ) =Ax + Bx B(t + ) = A x y = Ax + Bx State table 2
38 State diagram State transition diagram a circle: a state a directed lines connecting the circles: the transition between the states Each directed line is labeled inputs/outputs state: A B input: x
39 FlipFlop Input Equations The part of circuit that generates the inputs to flipflops Also called excitation functions DA = Ax +Bx DB = A'x The output equations to fully describe the sequential circuit y = (A+B)x' Ax Bx A 'x A+B Ax +Bx
40 Analysis with D flipflops The input equation D A =A x y The state equation A(t+)=A x y
41 J A = B, K A = Bx' J B = x ', K B = A' x + Ax Analysis with JK flipflops Determine the flipflop input function in terms of the present state and input variables Used the corresponding flipflop characteristic table to determine the next state Fig. 58 Sequential circuit with JK flipflop
42 State Table for Fig. 58 J A = B, K A = Bx' J B = x ', K B = A' x + Ax '
43 Method State Transition Diagram for Fig. 58 The characteristic equation of JK FF is A( t+ ) = JA + KA A A B( t+ ) = JB + KB B B State equation for A and B: A( t + ) = BA + ( Bx ) A = A B + AB + Ax Bt ( + ) = xb + ( A x) B= Bx + ABx+ ABx Method 2 x AB A(t +) AB A B Ax Using Kmap, we also can derive A(t+). A(t +)=A B+AB +Ax
44 Analysis with T FlipFlops The characteristic equation Q(t+)= T Q = TQ'+T'Q
45 Finite State Machine (FSM) The inputs, outputs and states of a sequential circuit can be described as the FSM. There are two different FSMs: (a) Mealy machine: the outputs are functions of both the present state and inputs (b) Moore machine: the outputs are functions of the present state only
46 Mealy Machine vs. Moore Machine
47 State Reduction and Assignment State Reduction reductions on the number of flipflops and the number of gates a reduction in the number of states may result in a reduction in the number of flipflops How to reduce the necessary states? State reduction: does not guarantee a saving in #FFs or #gates
48 State Reduction state a a b c d e f f g f g a input output only the inputoutput sequences are important two circuits are equivalent have identical outputs for all input sequences the number of states is not important Fig State diagram
49 Equivalent States Two states are said to be equivalent for each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state one of them can be removed
50 Reducing State Table
51 Reduced Finite State Machine state a a b c d e d d e d e a input output
52 State Reduction the checking of each pair of states for possible equivalence can be done systematically (95) the unused states are treated as don'tcare condition fewer combinational gates This example: reduce to 7 states 5 states
53 State Assignment to minimize the cost of the combinational circuits (not easy certainly??) three possible binary state assignments
54 Binary Assignment any binary number assignment is satisfactory as long as each state is assigned a unique number both OK,,,, (OK v),,,, (OK v)
55 Binary code The Three Assignments nbit code for m states, 2 n >= m (n FFs) Gray code nbit code for m states, 2 n >= m (n FFs) More suitable for Kmap simplification (more possible lower power) Onehot mbit code for m states (m FFs) often used in control design
56 Design Procedure specification a state diagram (most challenging) state reduction if necessary assign binary values to the states obtain the binarycoded state table choose the type of flipflops derive the simplified flipflop input equations and output equations draw the logic diagram Synthesis The part of design that follows a welldefined procedure is called synthesis Once a spec has been set down and the state diagram obtained, it is possible to use known synthesis procedure to complete the design
57 Synthesis using D flipflops (/2) An example state diagram and state table Design a circuit that detects one to three or more consecutive s in a input string m m m 2 m 3 m 4 m 5 m 6 m 7
58 Synthesis using D flipflops (2/2) The flipflop input equations () A(t+) = D A (A,B,x) = (3,5,7) (2) B(t+) = D B (A,B,x) = (,5,7) The output equation (3) y(a,b,x) = (6,7) Logic minimization using three K maps
59 Logic Diagram of Sequence Detector with D FF FF Input eqs. D A (A,B,x)= Ax+Bx D B (A,B,x)= Ax+B x Output eq. y(a,b,x)= AB Ax+Bx Ax+B x AB back
60 Synthesis using JK flipflops (/4) A state diagram flipflop input functions straightforward for D flipflops we need excitation tables for JK and T flipflops J K D Q(t+) Function Q(t) Q(t) no change reset FF to set FF to Q (t) Q (t) complement output T D Q(t+) Q Q(t) no change Q Q (t) complement
61 Synthesis using JK flipflops (2/4) The same example The state table and JK flipflop inputs
62 Synthesis using JK flipflops (3/4)
63 Synthesis using JK flipflops (4/4) Compare with D flipflop
64 Synthesis using T flipflops A nbit binary counter the state diagram no inputs (except for the clock input)
65 The state table and the flipflop inputs No inputs (except for the clock input)
66 Logic Simplification using the K map
67 The Logic Diagram How to trace? Note:
68 Moore Machine (/4) Design description or timing diagram Develop state diagram Develop nextstate and output tables Minimize states Encode input, states, and outputs Decide the memory elements Optimization flow Derive excitation equation Optimize logic circuit Derive logic schematic and timing diagram Simulation Functional verification and timing analysis S O Present State S : state O Next State Output I= I= I= I= S S S 2 S S S 2 S 2 S 2 S 3 S 3 S 3 S :output Nextstate and output tables (I=input) / S / S S 2 S 3 / / / / / /
69 Moore Machine (2/4) Present State Next State Output I= I= I= I= S S S 2 S S S 2 S 2 S 2 S 3 S 3 S 3 S characteristic table J Q(t) K Q(t+) original state table Q(t+) Q(t) Q (t) excitation table J X X K X X I Present State M(t) N(t) Assume that we use JK flipflops for storage 4 states need 2 flipflops (named M and N) J Clk K Next State M(t+) N(t+) M MJ X X X X Q M(JK) MK X X X X J Clk K NJ X X X X N(JK) N NK X X X X Q Output
70 Moore Machine (3/4) MN I X X X X MN I X X X X MN I I Next state logic MJ=I MK=NI MN I X X MN Output=M N+MN N+MN Clk Clk J K J K X X NJ=MI I M N X X State register Q Q X X NK=M Output Output logic
71 Moore Machine (4/4) How about D FlipFlop? D Clk D A Q Which implementation is better? D Clk D B Q I Present State Next State A B A B Output AB I AB So, D A = I So, D B = Output is the same as JK implementation.
72 Video Tape Player (/2) Stop_Button Pause_Button Forward_Button Rewind_Button Play_Button Record_Button Reset clk Video Tape Player Stop_Tape Pause_Tape Forward_Tape Rewind_Tape Play_Tape Record_Tape
73 Video Tape Player (2/2) Reset= Stop_Button= Stop Stop_Tape = Forward_Button= Record_Button= & Play_Button= Will_Forward Stop_Tape= Will_Record Stop_Tape= Forward Forward_Tape= Record Record_Tape= Will_Play Play_Button= Stop_Tape= Will_Rewind Rewind_Button= Stop_Tape= Play Play_Tape = Rewind Rewind_Tape= Pause_Button= Pause_Button= Pause Pause_Tape =
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