ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies


 Emery Lester Williams
 3 years ago
 Views:
Transcription
1 ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher
2 Asynchronous Counter Operation A 2Bit Asynchronous Binary Counter This counter is asynchronous because there is no common clock pulse. The clocks are cascaded Clock Pulse Q1 Q0 Initially (recycles) 0 0
3 Asynchronous Counter Operation A 3Bit Asynchronous Binary Counter
4 Asynchronous Counter Operation Propagation Delay One issue with asynchronous counters is propagation delay due to the ripple effect. The clock pulse of successive stages is derived from the output of previous stages. This has a cumulative effect.
5 Asynchronous Counter Operation Asynchronous Decade Counters The modulus of a counter is the number of unique states through which the counter will sequence. A decade counter has 10 states which produces the BCD code. Since 4 stages are required to count to at least 10, the counter must be forced to recycle before going through all of its states (counts 1115) We can force this recycling by decoding the output and clear the flipflops when the count = 10 The glitch is a result of the need for Q1 to go high before it can be decoded. The width of the glitch is a function of the speed of the gate.
6 Asynchronous Counter Operation The 74LS93 4Bit Asynchronous Binary Counter This device is reset by taking both R0(1) and R0(2) high. It can be used as a divide by 2 counter by using only the first flipflop. It can be configured as a modulus16 counter (counts 015) by connecting the Q0 output back to the CLK B input It can be configured as a modulus10 counter (decade) by partial decoding of count 10 (connect Q0 to CLK B, Q1 to Ro(1) and Q3 to R0(2).
7 Synchronous Counter Operation Synchronous counters have a common clock pulse applied simultaneously to all flipflops. A 2Bit Synchronous Binary Counter Inputs Outputs Comments J K CLK Q Q 0 0 Q0 Q0 No change RESET SET 1 1 Q0 Q0 Toggle Note that both the J and K inputs are connected together. The flipflop will toggle when both are a 1 (FF0) Also the transition at clock pulse 2 works because of propagation delay effects. Q0 is still high on the input of Q1 at the instant clock 2 hits so FF1 changes state. A short time later clock 2 has propagated through FF0 and it goes low.
8 Synchronous Counter Operation A 3Bit Synchronous Binary Counter
9 Synchronous Counter Operation A 4Bit Synchronous Binary Counter Note: The shaded areas are where the AND gates are HIGH.
10 Synchronous Counter Operation A 4Bit Synchronous Decade Counter (BCD)
11 Synchronous Counter Operation The 74HC163 4Bit Synchronous Binary Counter This IC also has the capability of presetting the count to any valid binary value. Note also the asynchronous CLR.
12 Synchronous Counter Operation The 74F162 Synchronous BCD Decade Counter
13 Up/Down Synchronous Counters Many applications require a counter that can be decremented as well as incremented These are also known as bidirectional counters and they can have any specified sequence of states. The direction is controlled by an additional input pin that when held HIGH makes it count up and when held LOW it counts down. The direction of counting can be reversed at any point (by changing the state of the up/down pin).
14 Up/Down Synchronous Counters Typical 3Bit Up/Down Counter
15 Up/Down Synchronous Counters The 74HC190 Up/Down Decade Counter
16 Design of Synchronous Counters We can use synchronous counting circuits to implement state machines. State machines are useful in many control and digital applications as they provide the means for taking specific action based upon what state the machine is in and, perhaps, some external event. Two types of state machines Moore Circuits the outputs depend only on the present internal state Mealy Circuits the output depends on the present state and one or more inputs. State machines are sequential in that they follow prescribed paths. But the path may vary depending on events.
17 Design of Synchronous Counters General Model of a Sequential Circuit Memory circuits are flipflops. They are always in one state or another. The state they are in is called the present state. When they change, they go to the next state. Inputs will affect the path the circuit takes to the next state. The present state of the output variables Q0 through Qn define the value of the state they are in. Note that the logic section also looks at the output as well as the input.
18 Design of Synchronous Counters Step 1: State Diagram Shows the progression through the states Note that there is a direction to each path This circuit only has a clock input It can only go through one set path It does not respond to external events. Each circle defines a state The numbers inside are the values of the state variables (outputs)
19 Design of Synchronous Counters Step 2: NextState Table This table is derived from the state diagram as shown on the previous slide. Q0 is the LSB, Q3 is the MSB These represent the current value of the state variables. These represent the next value of the state variables after the next clock pulse.
20 Design of Synchronous Counters Step 3: FlipFlop Transition Table All possible output transitions are listed as they transition from the present state to the next state. For each output transition, the J and K inputs that will cause the transition to occur are shown. An X indicates a don't care condition. Use the transition table to design the counter by applying it to each of the flip flops in the counter.
21 Design of Synchronous Counters Step 4: Karnaugh Maps A Karnaugh map is created for the J and K inputs. Each cell represents one of the present states of the counter (the left side of the NextState table). Place a 1 or 0 in each cell depending on the transition of the Q output (from the right side of the NextState table). So, each cell is the present state, but the value it holds is for the next state. FlipFlop Transition Table J0 Map NextState Table This mapping is performed for each row in the Next State table. K0 Map
22 Design of Synchronous Counters Karnaugh maps for 3bit Gray Code Counter
23 Design of Synchronous Counters Step 5: Logic Expressions for FlipFlop Inputs The SOP terms for each stage are derived from the Karnaugh Maps: J 0 =Q 2 Q 1 Q 2 Q 1=Q 2 XOR Q 1 K 0=Q 2 Q 1 Q 2 A1=Q 2 XOR Q 1 J 1=Q 2 Q 0 K 1=Q 2 Q 0 J 2=Q 1 Q 0 K 2=Q 1 Q 0 Step 6: Counter Implementation
24 Cascaded Counters Cascading counters connects them in series with the output of one becoming the input of the other. This provides a means of achieving highermodulus operation Cascading a mod4 and mod8 counter yields a mod32 counter. Note that the mod number is 2 raised to the number of output lines => 25 = 32 There are 32 unique states for this counter. This counter counts in binary.
25 Cascaded Counters Cascading is not limited to binary counters A modulus 100 counter from two decade counters. A divide by 1000 frequency divider.
26 Cascaded Counters Cascaded Counters with Truncated Sequences Any count value can be achieved by forcing a counter to: reset either before it reaches its full count preloading a specific value and then resetting to this value when full count is reached. The LOAD signal goes true when the terminal count is reached. This loads the values on the D inputs into each counter. The counters then count from this value up to the terminal value: ( ) Select a counter configuration that counts higher than you want to go Subtract the number of counts you want from the terminal count. Use this value as the preload value for the counters.
27 Counter Decoding Certain count values may need to be extracted from a counter This is done by using decoding logic to test for the particular value These decoded values can be used for events for other logic circuits. Fore some reason a signal is needed when this counter reaches a value of 6. The 3input AND gate will go HIGH when the counter is 6 (110) Using this scheme, any number of states can be decoded. Decoder chips may also be used instead of standard logic.
28 Counter Decoding Decoding Glitches As discussed before, glitches creep into the signals due to propagation delays even in synchronous circuits. These glitches need to be avoided since the decoding logic is usually fast enough to detect them Note the glitches introduced by propagation delay.
29 Counter Decoding Avoiding Glitches Strobe the enable input of the decoding logic chips This allows enough time to elapse after the clock pulse is applied for the chip to be at a steady value Note that the CLK pulse also acts as a LOW true Enable pulse for the decoder logic.
30 Counter Applications Many applications use counters Digital Clocks Automobile Parking Control ParalleltoSerial Data Conversion A/D Converters Frequency Meters/Counters Signal Generators Microprocessors These examples are in the book
31 Logic Symbols with Dependency Notation Alternative logic symbols defined by the ANSI/IEEE Usually they are similar to the traditional symbols but counters are one case where they are different. Qualifying Symbol Common Control Block Mode Dependency AND Dependency Control Dependency Individual Elements
32 Timing Logic with Software Using fixedfunction logic for timing can get complex and involved All that is available are flipflops and counters along with oneshots Programmable logic devices provide the ability to create software defined timing using text entry or schematic entry. Text entry using VHDL is more convenient in many cases. Schematic Entry Examples Divideby1,048,576 implemented with flipflops Divideby1,000,000 implemented with decade counters
33 Timing Logic with Software VHDL code can also be used to implement functions The divideby1,000,000 counter implemented with VHDL. The program keeps checking the value of the variable DelayCount. When it reaches 1,000,000, the variable ClockOut is set to a 1 and DelayCount is reset to 0. When the next event is detected, ClockOut is reset to a 0. This results in an output pulse beginning on the onemillionth input pulse and ending on the following input pulse.
34 Timing Logic with Software Timers Timers produce an output pulse of a specific duration Oneshots are usually used for this but are not available in the function library for programmable devices. Timers are created using VHDL General timer configuration with mod8 counter. Two separate timer definitions (4 sec. & 25 sec) using VHDL
Digital Fundamentals
Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationDIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
More informationContents COUNTER. Unit III Counters
COUNTER Contents COUNTER...1 Frequency Division...2 Divideby2 Counter... 3 Toggle FlipFlop...3 Frequency Division using Toggle Flipflops...5 Truth Table for a 3bit Asynchronous Up Counter...6 Modulo
More informationAsynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
More informationChapter 9 Latches, FlipFlops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, FlipFlops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationCascaded Counters. Page 1 BYU
Cascaded Counters Page 1 ModN Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A modn counter has N states Counts from 0 to N1 then rolls
More informationTo design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
More informationDIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
More informationCounters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of ModuloN ripple counter, UpDown counter, design of synchronous counters with and without
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationChapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters TFF Basic Counting element State
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4bit ripplethrough decade counter with a decimal readout display. Such a counter
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationFig11 2bit asynchronous counter
Digital electronics 1Sequential circuit counters Such a group of flip flops is a counter. The number of flipflops used and the way in which they are connected determine the number of states and also
More informationAsynchronous counters, except for the first block, work independently from a system clock.
Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flipflops, they can be asynchronous or synchronous and they can
More informationCounters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flipflop values themselves, serves as the output. The output value increases by one on each clock cycle.
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationDigital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian Email: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief Email: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An nbit register
More informationCounters are sequential circuits which "count" through a specific state sequence.
Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:
More informationNOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual InLine Package.
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo6
More informationCHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS
CHAPTER IX1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249275 FROM MANO AN KIME CHAPTER IX2 INTROUCTION INTROUCTION Like combinational building blocks, we can also develop
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. PuJen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits PuJen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationChapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7 Registers and Load Enable 72 Register Transfers 73 Register Transfer Operations 74 A Note for VHDL and Verilog Users
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationLecture3 MEMORY: Development of Memory:
Lecture3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationRegisters & Counters
Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multibit storage devices. Introduce counters by adding logic to registers implementing
More informationDesign Example: Counters. Design Example: Counters. 3Bit Binary Counter. 3Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationDecimal Number (base 10) Binary Number (base 2)
LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate Kmaps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationDigital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
More informationLab 1: Study of Gates & Flipflops
1.1 Aim Lab 1: Study of Gates & Flipflops To familiarize with circuit implementations using ICs and test the behavior of different logic gates and Flipflops. 1.2 Hardware Requirement a. Equipments 
More informationWiki Lab Book. This week is practice for wiki usage during the project.
Wiki Lab Book Use a wiki as a lab book. Wikis are excellent tools for collaborative work (i.e. where you need to efficiently share lots of information and files with multiple people). This week is practice
More informationBINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
More information74F168*, 74F169 4bit up/down binary synchronous counter
INTEGRATED CIRCUITS 74F168*, * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 5 IC15 Data Handbook FEATURES Synchronous counting and loading Up/Down counting
More information6BIT UNIVERSAL UP/DOWN COUNTER
6BIT UNIVERSAL UP/DOWN COUNTER FEATURES DESCRIPTION 550MHz count frequency Extended 100E VEE range of 4.2V to 5.5V Lookaheadcarry input and output Fully synchronous up and down counting Asynchronous
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationA Lesson on Digital Clocks, One Shots and Counters
A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates PowerOn Reset Circuits One Shots Counters
More informationA Lesson on Digital Clocks, One Shots and Counters
A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates PowerOn Reset Circuits One Shots Counters
More informationFlipFlops and Sequential Circuit Design. ECE 152A Winter 2012
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationFlipFlops and Sequential Circuit Design
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationEXPERIMENT 8. FlipFlops and Sequential Circuits
EXPERIMENT 8. FlipFlops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flipflops and counters.
More informationDEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS453
More informationSystems I: Computer Organization and Architecture
Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flipflops. Each flipflop stores one bit of data; n flipflops are required to store
More informationSequential Logic Design Principles.Latches and FlipFlops
Sequential Logic Design Principles.Latches and FlipFlops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and FlipFlops SR Latch
More informationIE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines
More information74LS193 Synchronous 4Bit Binary Counter with Dual Clock
74LS193 Synchronous 4Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4bit binary counter. Synchronous operation is provided by having all flipflops
More informationTakeHome Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas
TakeHome Exercise Assume you want the counter below to count mod6 backward. That is, it would count 0543210, etc. Assume it is reset on startup, and design the wiring to make the counter count
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flipflops;
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationUpon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationGray Code Generator and Decoder by Carsten Kristiansen Napier University. November 2004
Gray Code Generator and Decoder by Carsten Kristiansen Napier University November 2004 Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Design of a Gray Code Generator and
More informationChapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
More informationDigital Fundamentals
igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage
More informationDM74LS169A Synchronous 4Bit Up/Down Binary Counter
Synchronous 4Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry lookahead for cascading in highspeed counting applications. Synchronous operation
More informationOperating Manual Ver.1.1
4 Bit Binary Ripple Counter (UpDown Counter) Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94101, Electronic Complex Pardesipura, Indore 452010, India Tel : 91731 2570301/02, 4211100 Fax: 91731
More informationNOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual InLine Package.
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4BIT BINARY UP/DOWN COUNTERS The SN54/74LS190 is a synchronous UP/DOWN BCD Decade (8421) Counter and the SN54/74LS191 is a synchronous UP/DOWN Modulo
More informationDigital Fundamentals. Lab 8 Asynchronous Counter Applications
Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003). Horne Rev. 2 (1/2008). Bradbury Digital Fundamentals CETT 1425 Lab 8 Asynchronous Counter Applications Name: Date: Objectives:
More informationDATA SHEET. HEF40193B MSI 4bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationFinite State Machine. RTL Hardware Design by P. Chu. Chapter 10 1
Finite State Machine Chapter 10 1 Outline 1. Overview 2. FSM representation 3. Timing and performance of an FSM 4. Moore machine versus Mealy machine 5. VHDL description of FSMs 6. State assignment 7.
More informationDigital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
More information8254 PROGRAMMABLE INTERVAL TIMER
PROGRAMMABLE INTERVAL TIMER Y Y Y Compatible with All Intel and Most Other Microprocessors Handles Inputs from DC to 10 MHz 8 MHz 8254 10 MHz 82542 Status ReadBack Command Y Y Y Y Y Six Programmable
More information74AC191 Up/Down Counter with Preset and Ripple Clock
74AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED 2nd (Spring) term 22/23 5. LECTURE: REGISTERS. Storage registers 2. Shift
More informationDM74LS191 Synchronous 4Bit Up/Down Counter with Mode Control
August 1986 Revised February 1999 DM74LS191 Synchronous 4Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation
More informationList of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC7447).
G. H. RAISONI COLLEGE OF ENGINEERING, NAGPUR Department of Electronics & Communication Engineering Branch:4 th Semester[Electronics] Subject:  Digital Circuits List of Experiment Sr. Name Of Experiment
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationSN54/74LS192 SN54/74LS193
PRESEABLE BCD/DECADE UP/DOWN COUNER PRESEABLE 4BI BINARY UP/DOWN COUNER he SN4/74LS2 is an UP/DOWN BCD Decade (842) Counter and the SN4/74LS3 is an UP/DOWN MODULO6 Binary Counter. Separate Count Up and
More informationThe components. E3: Digital electronics. Goals:
E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7segment display. 2 st. IC
More informationSEQUENTIAL CIRCUITS. Block diagram. Flip Flop. SR Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationChapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
More informationModeling Sequential Elements with Verilog. Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 41 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationMICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1
MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable
More informationFINITE STATE MACHINE: PRINCIPLE AND PRACTICE
CHAPTER 10 FINITE STATE MACHINE: PRINCIPLE AND PRACTICE A finite state machine (FSM) is a sequential circuit with random nextstate logic. Unlike the regular sequential circuit discussed in Chapters 8
More informationENEE 244 (01**). Spring 2006. Homework 5. Due back in class on Friday, April 28.
ENEE 244 (01**). Spring 2006 Homework 5 Due back in class on Friday, April 28. 1. Fill up the function table (truth table) for the following latch. How is this latch related to those described in the lectures
More informationDM74LS193 Synchronous 4Bit Binary Counter with Dual Clock
September 1986 Revised March 2000 DM74LS193 Synchronous 4Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4bit binary counter. Synchronous operation
More informationDM54161 DM74161 DM74163 Synchronous 4Bit Counters
DM54161 DM74161 DM74163 Synchronous 4Bit Counters General Description These synchronous presettable counters feature an internal carry lookahead for application in highspeed counting designs The 161
More informationModeling Latches and Flipflops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit  FSM A Sequential circuit contains: Storage
More informationCopyright Peter R. Rony 2009. All rights reserved.
Experiment No. 1. THE DIGI DESIGNER Experiment 11. Socket Connections on the Digi Designer Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2INPUT POSITIVE NAND GATE Experiment 21. Truth Table
More informationCS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flipflops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More information18008314242
Distributed by: www.jameco.com 18008314242 The content and copyrights of the attached material are the property of its owner. DM74LS161A DM74LS163A Synchronous 4Bit Binary Counters General Description
More information54191 DM54191 DM74191 Synchronous Up Down 4Bit Binary Counter with Mode Control
54191 DM54191 DM74191 Synchronous Up Down 4Bit Binary Counter with Mode Control General Description This circuit is a synchronous reversible up down counter The 191 is a 4bit binary counter Synchronous
More informationState Machines in VHDL
State Machines in VHDL Implementing state machines in VHDL is fun and easy provided you stick to some fairly well established forms. These styles for state machine coding given here is not intended to
More informationSN54HC191, SN74HC191 4BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
Single Down/Up CountControl Line LookAhead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIPFLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1
More information(1) /30 (2) /30 (3) /40 TOTAL /100
Your Name: SI Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY AVIS IRVINE LOS ANGELES RIVERSIE SAN IEGO SAN FRANCISCO epartment of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA
More informationPLL frequency synthesizer
ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 4 Lab 4: PLL frequency synthesizer 1.1 Goal The goals of this lab exercise are:  Verify the behavior of a and of a complete PLL  Find capture
More information54LS169 DM54LS169A DM74LS169A Synchronous 4Bit Up Down Binary Counter
54LS169 DM54LS169A DM74LS169A Synchronous 4Bit Up Down Binary Counter General Description This synchronous presettable counter features an internal carry lookahead for cascading in highspeed counting
More information