ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

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1 ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher

2 Asynchronous Counter Operation A 2-Bit Asynchronous Binary Counter This counter is asynchronous because there is no common clock pulse. The clocks are cascaded Clock Pulse Q1 Q0 Initially (recycles) 0 0

3 Asynchronous Counter Operation A 3-Bit Asynchronous Binary Counter

4 Asynchronous Counter Operation Propagation Delay One issue with asynchronous counters is propagation delay due to the ripple effect. The clock pulse of successive stages is derived from the output of previous stages. This has a cumulative effect.

5 Asynchronous Counter Operation Asynchronous Decade Counters The modulus of a counter is the number of unique states through which the counter will sequence. A decade counter has 10 states which produces the BCD code. Since 4 stages are required to count to at least 10, the counter must be forced to recycle before going through all of its states (counts 1115) We can force this recycling by decoding the output and clear the flip-flops when the count = 10 The glitch is a result of the need for Q1 to go high before it can be decoded. The width of the glitch is a function of the speed of the gate.

6 Asynchronous Counter Operation The 74LS93 4-Bit Asynchronous Binary Counter This device is reset by taking both R0(1) and R0(2) high. It can be used as a divide by 2 counter by using only the first flip-flop. It can be configured as a modulus-16 counter (counts 0-15) by connecting the Q0 output back to the CLK B input It can be configured as a modulus-10 counter (decade) by partial decoding of count 10 (connect Q0 to CLK B, Q1 to Ro(1) and Q3 to R0(2).

7 Synchronous Counter Operation Synchronous counters have a common clock pulse applied simultaneously to all flip-flops. A 2-Bit Synchronous Binary Counter Inputs Outputs Comments J K CLK Q Q 0 0 Q0 Q0 No change RESET SET 1 1 Q0 Q0 Toggle Note that both the J and K inputs are connected together. The flip-flop will toggle when both are a 1 (FF0) Also the transition at clock pulse 2 works because of propagation delay effects. Q0 is still high on the input of Q1 at the instant clock 2 hits so FF1 changes state. A short time later clock 2 has propagated through FF0 and it goes low.

8 Synchronous Counter Operation A 3-Bit Synchronous Binary Counter

9 Synchronous Counter Operation A 4-Bit Synchronous Binary Counter Note: The shaded areas are where the AND gates are HIGH.

10 Synchronous Counter Operation A 4-Bit Synchronous Decade Counter (BCD)

11 Synchronous Counter Operation The 74HC163 4-Bit Synchronous Binary Counter This IC also has the capability of presetting the count to any valid binary value. Note also the asynchronous CLR.

12 Synchronous Counter Operation The 74F162 Synchronous BCD Decade Counter

13 Up/Down Synchronous Counters Many applications require a counter that can be decremented as well as incremented These are also known as bidirectional counters and they can have any specified sequence of states. The direction is controlled by an additional input pin that when held HIGH makes it count up and when held LOW it counts down. The direction of counting can be reversed at any point (by changing the state of the up/down pin).

14 Up/Down Synchronous Counters Typical 3-Bit Up/Down Counter

15 Up/Down Synchronous Counters The 74HC190 Up/Down Decade Counter

16 Design of Synchronous Counters We can use synchronous counting circuits to implement state machines. State machines are useful in many control and digital applications as they provide the means for taking specific action based upon what state the machine is in and, perhaps, some external event. Two types of state machines Moore Circuits the outputs depend only on the present internal state Mealy Circuits the output depends on the present state and one or more inputs. State machines are sequential in that they follow prescribed paths. But the path may vary depending on events.

17 Design of Synchronous Counters General Model of a Sequential Circuit Memory circuits are flipflops. They are always in one state or another. The state they are in is called the present state. When they change, they go to the next state. Inputs will affect the path the circuit takes to the next state. The present state of the output variables Q0 through Qn define the value of the state they are in. Note that the logic section also looks at the output as well as the input.

18 Design of Synchronous Counters Step 1: State Diagram Shows the progression through the states Note that there is a direction to each path This circuit only has a clock input It can only go through one set path It does not respond to external events. Each circle defines a state The numbers inside are the values of the state variables (outputs)

19 Design of Synchronous Counters Step 2: Next-State Table This table is derived from the state diagram as shown on the previous slide. Q0 is the LSB, Q3 is the MSB These represent the current value of the state variables. These represent the next value of the state variables after the next clock pulse.

20 Design of Synchronous Counters Step 3: Flip-Flop Transition Table All possible output transitions are listed as they transition from the present state to the next state. For each output transition, the J and K inputs that will cause the transition to occur are shown. An X indicates a don't care condition. Use the transition table to design the counter by applying it to each of the flip flops in the counter.

21 Design of Synchronous Counters Step 4: Karnaugh Maps A Karnaugh map is created for the J and K inputs. Each cell represents one of the present states of the counter (the left side of the Next-State table). Place a 1 or 0 in each cell depending on the transition of the Q output (from the right side of the Next-State table). So, each cell is the present state, but the value it holds is for the next state. Flip-Flop Transition Table J0 Map Next-State Table This mapping is performed for each row in the Next State table. K0 Map

22 Design of Synchronous Counters Karnaugh maps for 3-bit Gray Code Counter

23 Design of Synchronous Counters Step 5: Logic Expressions for Flip-Flop Inputs The SOP terms for each stage are derived from the Karnaugh Maps: J 0 =Q 2 Q 1 Q 2 Q 1=Q 2 XOR Q 1 K 0=Q 2 Q 1 Q 2 A1=Q 2 XOR Q 1 J 1=Q 2 Q 0 K 1=Q 2 Q 0 J 2=Q 1 Q 0 K 2=Q 1 Q 0 Step 6: Counter Implementation

24 Cascaded Counters Cascading counters connects them in series with the output of one becoming the input of the other. This provides a means of achieving higher-modulus operation Cascading a mod-4 and mod-8 counter yields a mod-32 counter. Note that the mod number is 2 raised to the number of output lines => 25 = 32 There are 32 unique states for this counter. This counter counts in binary.

25 Cascaded Counters Cascading is not limited to binary counters A modulus 100 counter from two decade counters. A divide by 1000 frequency divider.

26 Cascaded Counters Cascaded Counters with Truncated Sequences Any count value can be achieved by forcing a counter to: reset either before it reaches its full count pre-loading a specific value and then resetting to this value when full count is reached. The LOAD signal goes true when the terminal count is reached. This loads the values on the D inputs into each counter. The counters then count from this value up to the terminal value: ( ) Select a counter configuration that counts higher than you want to go Subtract the number of counts you want from the terminal count. Use this value as the pre-load value for the counters.

27 Counter Decoding Certain count values may need to be extracted from a counter This is done by using decoding logic to test for the particular value These decoded values can be used for events for other logic circuits. Fore some reason a signal is needed when this counter reaches a value of 6. The 3input AND gate will go HIGH when the counter is 6 (110) Using this scheme, any number of states can be decoded. Decoder chips may also be used instead of standard logic.

28 Counter Decoding Decoding Glitches As discussed before, glitches creep into the signals due to propagation delays even in synchronous circuits. These glitches need to be avoided since the decoding logic is usually fast enough to detect them Note the glitches introduced by propagation delay.

29 Counter Decoding Avoiding Glitches Strobe the enable input of the decoding logic chips This allows enough time to elapse after the clock pulse is applied for the chip to be at a steady value Note that the CLK pulse also acts as a LOW true Enable pulse for the decoder logic.

30 Counter Applications Many applications use counters Digital Clocks Automobile Parking Control Parallel-to-Serial Data Conversion A/D Converters Frequency Meters/Counters Signal Generators Microprocessors These examples are in the book

31 Logic Symbols with Dependency Notation Alternative logic symbols defined by the ANSI/IEEE Usually they are similar to the traditional symbols but counters are one case where they are different. Qualifying Symbol Common Control Block Mode Dependency AND Dependency Control Dependency Individual Elements

32 Timing Logic with Software Using fixed-function logic for timing can get complex and involved All that is available are flip-flops and counters along with one-shots Programmable logic devices provide the ability to create software defined timing using text entry or schematic entry. Text entry using VHDL is more convenient in many cases. Schematic Entry Examples Divide-by-1,048,576 implemented with flip-flops Divide-by-1,000,000 implemented with decade counters

33 Timing Logic with Software VHDL code can also be used to implement functions The divide-by-1,000,000 counter implemented with VHDL. The program keeps checking the value of the variable DelayCount. When it reaches 1,000,000, the variable ClockOut is set to a 1 and DelayCount is reset to 0. When the next event is detected, ClockOut is reset to a 0. This results in an output pulse beginning on the one-millionth input pulse and ending on the following input pulse.

34 Timing Logic with Software Timers Timers produce an output pulse of a specific duration One-shots are usually used for this but are not available in the function library for programmable devices. Timers are created using VHDL General timer configuration with mod-8 counter. Two separate timer definitions (4 sec. & 25 sec) using VHDL