Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010


 Britton Lawson
 3 years ago
 Views:
Transcription
1 EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
2 Sequencing Outline Sequencing Element esign Max and Minelay Clock Skew 10.2 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
3 Combinational logic Sequencing output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in out CL CL CL Finite State Machine Pipeline 10.3 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
4 Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiberoptic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
5 Sequencing Overhead Use flipflops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 10.5 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
6 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flipflop: edge triggered A.k.a. masterslave flipflop, flipflop, register Timing iagrams Transparent Opaque Edgetrigger Latch Flop (latch) (flop) 10.6 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
7 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flipflop: edge triggered A.k.a. masterslave flipflop, flipflop, register Timing iagrams Transparent Opaque Edgetrigger Latch Flop (latch) (flop) 10.7 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
8 Latch esign Pass Transistor Latch Pros +Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s 10.8 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
9 Latch esign Transmission gate +No V t drop  Requires inverted clock 10.9 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
10 Latch esign Inverting buffer +Restoring + No backdriving X + Fixes either Output noise sensitivity Or diffusion input Inverted output Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
11 Latch esign Tristate feedback + Static Backdriving risk X Static latches are now essential Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
12 Latch esign Buffered input + Fixes diffusion input + Noninverting X Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
13 Latch esign Buffered output + No backdriving X Widely used in standard cells + Very robust (most important)  Rather large  Rather slow (1.5 2 FO4 delays)  High clock loading Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
14 atapath latch Latch esign + Smaller, faster  unbuffered input X Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
15 FlipFlop esign Flipflop is built as pair of backtoback latches X X Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
16 Enable Enable: ignore clock when en = 0 Mux: increase latch  delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 0 Latch Latch en en en F lop 1 0 en Flop lop F en Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
17 Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Re eset reset reset Asynchronous Reset reset reset reset reset Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
18 Set / Reset Set forces output high when enabled Flipflop pwith asynchronous set and reset set reset reset set Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
19 Sequencing Methods Flipflops T c 2Phase Latches Pulsed Latches FlipFlo ops Flop Combinational Logic Flop 2Phase Transpar rent Latches 1 2 Latch T c /2 t nonoverlap Latch t nonoverlap Combinational Logic Combinational Logic HalfCycle 1 HalfCycle 1 Latch Pulsed Latches p t pw p Latc ch Combinational Logic p Latc ch Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
20 Timing iagrams Contamination and Propagation elays t pd t cd t pcq Logic Prop. elay Logic Cont. elay Latch/Flop Clk Prop elay A Combinational Logic Y A Y t cd t pd t ccq t pdq t pcq t setup Latch/Flop Clk Cont. elay Latch  Prop elay Latch  Cont. elay Latch/Flop Setup Time Flop t setup t ccq t hold t pcq t hold Latch/Flop Hold Time t setup t hold t t ccq pcq q Latch t cdq t pdq Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
21 Maxelay: FlipFlops ( setup ) tpd Tc t + tpcq sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
22 Max elay: Pulsed Latches ( setup ) tpd Tc max tpdq, tpcq + t tpw sequencing overhead p p 1 L1 1 Combinational Logic 2 L2 2 T c 1 t pdq (a) t pw > t setup 1 t t pd 2 p t pcq tpd tsetup T c t pw (b) t pw < t setup Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
23 Minelay: FlipFlops t t t cd hold ccq F1 1 CL 2 F2 1 t ccq t cd 2 t hold Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
24 Clock Skew We have assumed zero clock skew Two types of clock skews: Negative skew: sending register receives the clock earlier than the receiving register Positive skew: receiving register gets the clock earlier than the sending register. Clocks really have uncertainty t in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
25 Skew: FlipFlops ( setup skew ) tpd Tc tpcq + t + t sequencing overhead F1 1 Combinational Logic T c 2 F2 t t t + t cd hold ccq skew t pcq t skew 1 t pdq t setup 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010
Lecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Minelay q Clock Skew q Time Borrowing
More informationLecture 11: Sequential Circuit Design
Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Minelay Clock Skew Time Borrowing TwoPhase Clocking 2 Sequencing Combinational logic output depends on current
More informationSequential Circuits. Combinational Circuits Outputs depend on the current inputs
Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating
More informationSequential Circuit Design
Sequential Circuit Design LanDa Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines
More informationL4: Sequential Building Blocks (Flipflops, Latches and Registers)
L4: Sequential Building Blocks (Flipflops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
More informationIntroduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems
Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH
More informationWeste07r4.fm Page 183 Monday, January 5, 2004 1:39 AM. 7.1 Introduction
Weste07r4.fm Page 183 Monday, January 5, 2004 1:39 AM 7 7.1 Introduction The previous chapter addressed combinational circuits in which the output is a function of the current inputs. This chapter discusses
More informationLecture 7: Clocking of VLSI Systems
Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 TwoPhase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10  Clocking Note: The analysis
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flipflops;
More informationLatch Timing Parameters. Flipflop Timing Parameters. Typical Clock System. Clocking Overhead
Clock  key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationECE380 Digital Logic
ECE38 igital Logic FlipFlops, Registers and Counters: FlipFlops r.. J. Jackson Lecture 25 Flipflops The gated latch circuits presented are level sensitive and can change states more than once during
More informationClocking. Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 Clocks 1
ing Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884  Spring 2005 2/18/05
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationTiming Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
More informationSequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
More informationSequential Logic Design Principles.Latches and FlipFlops
Sequential Logic Design Principles.Latches and FlipFlops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and FlipFlops SR Latch
More informationMaster/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
More informationLecture3 MEMORY: Development of Memory:
Lecture3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
More informationTopics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology
Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Twophase clocking. Testing of combinational (Chapter 4) and sequential (Chapter
More informationCSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap 5, App. A& B) Number representations Boolean algebra OP and PO Logic
More informationLecture 10: Latch and FlipFlop Design. Outline
Lecture 1: Latch and FlipFlop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flipflops
More informationCHAPTER 11 LATCHES AND FLIPFLOPS
CHAPTER 11 LATCHES AND FLIPFLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 SetReset Latch 11.3 Gated D Latch 11.4 EdgeTriggered D FlipFlop 11.5 SR FlipFlop
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationSetReset (SR) Latch
eteset () Latch Asynchronous Level sensitive crosscoupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0? 0? Indeterminate crosscoupled Nand gates
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationModeling Sequential Elements with Verilog. Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 41 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationLayout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
More informationIntroduction to CMOS VLSI Design
Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, AddisonWesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration
More information7. Latches and FlipFlops
Chapter 7 Latches and FlipFlops Page 1 of 18 7. Latches and FlipFlops Latches and flipflops are the basic elements for storing information. One latch or flipflop can store one bit of information. The
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. PuJen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits PuJen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationTheory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
More informationCDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch EdgeTriggered D FlipFlop (FF) SR FlipFlop (FF) JK FlipFlop (FF) T FlipFlop
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationChapter 9 Latches, FlipFlops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, FlipFlops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit  FSM A Sequential circuit contains: Storage
More informationTo design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
More informationCS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on
CS 61C: Great Ideas in Computer Architecture Finite State Machines Instructors: Krste Asanovic & Vladimir Stojanovic hbp://inst.eecs.berkeley.edu/~cs61c/sp15 1 Levels of RepresentaKon/ InterpretaKon High
More informationThe enable pin needs to be high for data to be fed to the outputs Q and Q bar.
of 7 Type flipflop (Toggle switch) The type flipflops are used in prescalar/divider circuits and frequency phase detectors. Figure shows how the flipflop (latch) can be made using input logic circuits
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationChapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
More informationCounters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flipflop values themselves, serves as the output. The output value increases by one on each clock cycle.
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationAsynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
More informationDesign Verification & Testing Design for Testability and Scan
Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing
More informationSEQUENTIAL CIRCUITS. Block diagram. Flip Flop. SR Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate Kmaps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More information路 論 Chapter 15 SystemLevel Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 SystemLevel Physical Design Dept. of Electronic Engineering National ChinYi University of Technology Fall 2007 Outline Clocked Flipflops CMOS
More informationCounters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of ModuloN ripple counter, UpDown counter, design of synchronous counters with and without
More informationDIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
More informationDATA SHEET. HEF40193B MSI 4bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
More informationDIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
More informationChapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7 Registers and Load Enable 72 Register Transfers 73 Register Transfer Operations 74 A Note for VHDL and Verilog Users
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationDigital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian Email: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief Email: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An nbit register
More informationChapter 2 Clocks and Resets
Chapter 2 Clocks and Resets 2.1 Introduction The cost of designing ASICs is increasing every year. In addition to the nonrecurring engineering (NRE) and mask costs, development costs are increasing due
More informationAsynchronous counters, except for the first block, work independently from a system clock.
Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flipflops, they can be asynchronous or synchronous and they can
More informationFlipFlops and Sequential Circuit Design. ECE 152A Winter 2012
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationFlipFlops and Sequential Circuit Design
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4bit ripplethrough decade counter with a decimal readout display. Such a counter
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationRegister File, Finite State Machines & Hardware Control Language
Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework
More informationModeling Latches and Flipflops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationChapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters TFF Basic Counting element State
More informationBINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
More information74LS193 Synchronous 4Bit Binary Counter with Dual Clock
74LS193 Synchronous 4Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4bit binary counter. Synchronous operation is provided by having all flipflops
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIPFLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1
More informationMM74HC4538 Dual Retriggerable Monostable Multivibrator
MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicongate CMOS technology. They feature
More informationDesign Example: Counters. Design Example: Counters. 3Bit Binary Counter. 3Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationCD4027BC Dual JK Master/Slave FlipFlop with Set and Reset
October 1987 Revised March 2002 CD4027BC Dual JK Master/Slave FlipFlop with Set and Reset General Description The CD4027BC dual JK flipflops are monolithic complementary MOS (CMOS) integrated circuits
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationPass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).
Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already
More informationContents COUNTER. Unit III Counters
COUNTER Contents COUNTER...1 Frequency Division...2 Divideby2 Counter... 3 Toggle FlipFlop...3 Frequency Division using Toggle Flipflops...5 Truth Table for a 3bit Asynchronous Up Counter...6 Modulo
More informationSequential 4bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationCS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flipflops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit A Sequential circuit contains: Storage elements:
More informationObsolete Product(s)  Obsolete Product(s)
SYNCHRONOUS PROGRAMMABLE 4BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOKAHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOWPOWER TTL COMPATIBILITY STANDARDIZED
More informationDigital Fundamentals
igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles or any text in boolean algebra Introduction We could design at the level of irsim
More informationA Lesson on Digital Clocks, One Shots and Counters
A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates PowerOn Reset Circuits One Shots Counters
More informationClass 11: Transmission Gates, Latches
Topics: 1. Intro 2. Transmission Gate Logic Design 3. XGate 2to1 MUX 4. XGate XOR 5. XGate 8to1 MUX 6. XGate Logic Latch 7. Voltage Drop of nch XGates 8. nch Pass Transistors vs. CMOS XGates
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence
More informationDM74LS169A Synchronous 4Bit Up/Down Binary Counter
Synchronous 4Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry lookahead for cascading in highspeed counting applications. Synchronous operation
More informationA Lesson on Digital Clocks, One Shots and Counters
A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates PowerOn Reset Circuits One Shots Counters
More informationDM74LS193 Synchronous 4Bit Binary Counter with Dual Clock
September 1986 Revised March 2000 DM74LS193 Synchronous 4Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4bit binary counter. Synchronous operation
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationTRIPLE D FLIPFLOP FEATURES DESCRIPTION PIN NAMES BLOCK DIAGRAM
TRIPLE D FLIPFLOP FEATURES DESCRIPTION Max. toggle frequency of 800MHz Differential outputs IEE min. of 80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = 4.2V to 5.5V Voltage
More informationDigital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
More informationThe components. E3: Digital electronics. Goals:
E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7segment display. 2 st. IC
More information