Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

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1 EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

2 Sequencing Outline Sequencing Element esign Max and Min-elay Clock Skew 10.2 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

3 Combinational logic Sequencing output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in out CL CL CL Finite State Machine Pipeline 10.3 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

4 Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

5 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 10.5 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

6 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Latch Flop (latch) (flop) 10.6 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

7 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Latch Flop (latch) (flop) 10.7 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

8 Latch esign Pass Transistor Latch Pros +Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s 10.8 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

9 Latch esign Transmission gate +No V t drop - Requires inverted clock 10.9 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

10 Latch esign Inverting buffer +Restoring + No backdriving X + Fixes either Output noise sensitivity Or diffusion input Inverted output Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

11 Latch esign Tristate feedback + Static Backdriving risk X Static latches are now essential Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

12 Latch esign Buffered input + Fixes diffusion input + Noninverting X Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

13 Latch esign Buffered output + No backdriving X Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

14 atapath latch Latch esign + Smaller, faster - unbuffered input X Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

15 Flip-Flop esign Flip-flop is built as pair of back-to-back latches X X Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

16 Enable Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 0 Latch Latch en en en F lop 1 0 en Flop lop F en Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

17 Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Re eset reset reset Asynchronous Reset reset reset reset reset Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

18 Set / Reset Set forces output high when enabled Flip-flop pwith asynchronous set and reset set reset reset set Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

19 Sequencing Methods Flip-flops T c 2-Phase Latches Pulsed Latches Flip-Flo ops Flop Combinational Logic Flop 2-Phase Transpar rent Latches 1 2 Latch T c /2 t nonoverlap Latch t nonoverlap Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 Latch Pulsed Latches p t pw p Latc ch Combinational Logic p Latc ch Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

20 Timing iagrams Contamination and Propagation elays t pd t cd t pcq Logic Prop. elay Logic Cont. elay Latch/Flop Clk- Prop elay A Combinational Logic Y A Y t cd t pd t ccq t pdq t pcq t setup Latch/Flop Clk- Cont. elay Latch - Prop elay Latch - Cont. elay Latch/Flop Setup Time Flop t setup t ccq t hold t pcq t hold Latch/Flop Hold Time t setup t hold t t ccq pcq q Latch t cdq t pdq Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

21 Max-elay: Flip-Flops ( setup ) tpd Tc t + tpcq sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

22 Max elay: Pulsed Latches ( setup ) tpd Tc max tpdq, tpcq + t tpw sequencing overhead p p 1 L1 1 Combinational Logic 2 L2 2 T c 1 t pdq (a) t pw > t setup 1 t t pd 2 p t pcq tpd tsetup T c t pw (b) t pw < t setup Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

23 Min-elay: Flip-Flops t t t cd hold ccq F1 1 CL 2 F2 1 t ccq t cd 2 t hold Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

24 Clock Skew We have assumed zero clock skew Two types of clock skews: Negative skew: sending register receives the clock earlier than the receiving register Positive skew: receiving register gets the clock earlier than the sending register. Clocks really have uncertainty t in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

25 Skew: Flip-Flops ( setup skew ) tpd Tc tpcq + t + t sequencing overhead F1 1 Combinational Logic T c 2 F2 t t t + t cd hold ccq skew t pcq t skew 1 t pdq t setup 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010

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