More Verilog. 8bit Register with Synchronous Reset. Shift Register Example. Nbit Register with Asynchronous Reset.


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1 More Verilog 8bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog  1 Verilog  2 Nbit Register with Asynchronous Reset Shift Register Example module regn (reset, CLK, D, Q); input reset; parameter N = 8; // Allow N to be changed input [N1:0] D; output [N1:0] Q; reg [N1:0] Q; CLK or posedge reset) if (reset) Q = 0; else if (CLK == 1) Q = D; module // regn // 8bit register can be cleared, loaded, shifted left // Retains value if no control signal is asserted module shiftreg (CLK, clr, shift, ld, Din, SI, Dout); input clr; // clear register input shift; // shift input ld; // load register from Din input [7:0] Din; // Data input for load input SI; // Input bit to shift in output [7:0] Dout; reg [7:0] Dout; if (clr) Dout <= 0; else if (ld) Dout <= Din; else if (shift) Dout <= { Dout[6:0], SI }; Verilog  3 module // shiftreg Verilog  4 Blocking and NonBlocking Assignments Swap (continued) Q = A " # $ Q <= A ' temp = B; B = A; A = temp; Verilog  5 A <= B; B <= A; A = B; ( posedge CLK A <= B; B = A; B <= A; Verilog  6
2 NonBlocking Assignment # $ ) $$ * $ +), +./" // this implements 3 parallel flipflops B = A; C = B; D = C; // this implements a shift register {D, C, B} = {C, B, A}; // this implements a shift register B <= A; C <= B; D <= C; Verilog  7 Counter Example // 8bit counter with clear and count enable controls module count8 (CLK, clr, cnten, Dout); input clr; // clear counter input cnten; // enable count output [7:0] Dout; // counter value reg [7:0] Dout; if (clr) Dout <= 0; else if (cnten) Dout <= Dout + 1; module Verilog  8 Finite State Machines Verilog FSM  Reduce 1s example Mealy outputs ' inputs combinational logic next state Moore outputs current state // State assignment parameter zero = 0, one1 = 1, two1s = 2; module reduce (clk, reset, in, out); input clk, reset, in; reg out; reg [1:0] state; // state register reg [1:0] next_state; 3 3 // Implement the state register if (reset) state = zero; else state = next_state; Verilog  9 Verilog  10 Moore Verilog FSM (cont d) Mealy Verilog FSM for Reduce1s example or state) case (state) // defaults next_state = zero; zero: // last input was a zero if (in) next_state = one1; one1: // we've seen one 1 if (in) next_state = two1s; two1s: // we've seen at least 2 ones out = 1; if (in) next_state = two1s; // Don t need case default because of default assignments case module module reduce (clk, reset, in, out); input clk, reset, in; reg out; reg state; // state register reg next_state; parameter zero = 0, one = 1; if (reset) state = zero; else state = next_state; or state) next_state = zero; case (state) zero: // last input was a zero if (in) next_state = one; one: // we've seen one 1 if (in) next_state = one; out = 1; case module Verilog  11 Verilog
3 Restricted FSM Implementation Style Singlealways Moore Machine (Not Recommed) " ) module reduce (clk, reset, in, out); input clk, reset, in; reg out; reg [1:0] state; // state register parameter zero = 0, one1 = 1, two1s = 2; Verilog  13 Verilog  14 Singlealways Moore Machine (Not Recommed) Delays case (state) zero: if (in) state = one1; else state = zero; one1: if (in) state = two1s; out = 1; else state = zero; two1s: if (in) state = two1s; out = 1; else state = zero; default: state = zero; case module Verilog  15 All outputs are registered This is confusing: the output does not change until the next clock cycle module and_gate (out, in1, in2); input in1, in2; assign #10 out = in1 in2; module Verilog Verilog Propagation Delay Initial Blocks assign #5 c = a b; assign #4 {Cout, S} = Cin + A + B; ) 0 or B or Cin) #4 S = A + B + Cin; #2 Cout = (A B) (B Cin) (A Cin); assign #3 zero = (sum == 0)? 1 : 0; if (sum == 0) #6 zero = 1; else #3 zero = 0; Verilog  17 Verilog  18
4 TriState Buffers Test Fixtures 9: 6$ $; module tstate (EnA, EnB, BusA, BusB, BusOut); input EnA, EnB; input [7:0] BusA, BusB; output [7:0] BusOut; < < = 11= 12 assign BusOut = EnA? BusA : 8 bz; assign BusOut = EnB? BusB : 8 bz; module Test Fixture (Specification) Simulation Circuit Description (Synthesizeable) Verilog  19 Verilog  20 Verilog Clocks Verilog Clocks > + module clockgenerator (CLK); parameter period = 10; parameter howlong = 100; output CLK; reg CLK; module clock_gen (masterclk); `define PERIOD = 10; " " initial CLK = 0; #(period/2); repeat (howlong) CLK = 1; #(periodperiod/2); CLK = 0; #(period/2); $finish; output masterclk; reg masterclk; initial masterclk = 0; always #`PERIOD/2 masterclk = ~masterclk; " # module // clockgenerator module Verilog  21 Verilog  22 Example Test Fixture Simulation Driver module stimulus (a, b, c); parameter delay = 10; module full_addr1 (A, B, Cin, S, Cout); output a, b, c; input A, B, Cin; reg [2:0] cnt; output S, Cout; initial assign {Cout, S} = A + B + Cin; cnt = 0; module repeat (8) #delay cnt=cnt+1; #delay $finish; assign {c, a, b} = cnt; module module driver; // Structural Verilog connects testfixture to full adder wire a, b, cin, sum, cout; stimulus stim (a, b, cin); full_addr1 fa1 (a, b, cin, sum, cout); initial $monitor time=0d cin=b, a=b, b=b, cout=d, sum=d", $time, cin, a, b, cout, sum); module Verilog  23 module stimulus (a, b); parameter delay = 10; output a, b; reg [1:0] cnt; initial cnt = 0; repeat (4) #delay cnt = cnt + 1; #delay $finish; assign {a, b} = cnt; module Verilog  24 $ # "
5 Test Vectors Verilog Simulation module testdata(clk, reset, data); input clk; output reset, data; reg [1:0] testvector [100:0]; reg reset, data; integer count; initial $readmemb("data.b", testvector); count = 0; { reset, data } = testvector[0]; count = count + 1; #1 { reset, data } = testvector[count]; module 32 ) 0? Verilog  25 Verilog  26 Intepreted vs. Compiled Simulation Simulation Level 3 "1 1 "1 = " 0 * ' " $ > $ $ Verilog  27 Verilog  28 Simulation Time and Event Queues Verilog Time '" AA " " " " " 0? $ " B $ 1221B //5 ", "1 = C Verilog  29 Verilog  30
6 Inertial and Transport Delays A few requirements for CSE DE/+F, D 1 + E E./8 D+F + E 1D $ $ + G E + ; $ 8 ) 1 ; 6) 0 Verilog  31 Verilog  32
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