CSE140: Components and Design Techniques for Digital Systems

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1 CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources:

2 Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic minimization using K-maps Two and multi-level implementation Hazards AOI, PAL, PLA, OM implementation Mux and emux Adders, Multipliers and ALUs What comes next: equential circuits 2

3 K-maps, hazards, muxes & NO-only F(A,B,C,)= Π M(2, 3, 6, 8, 9, 2, 3, 4) A C B 3

4 emultiplexers as general-purpose logic F = A'BC' + A'B'C + ABC F2 = ABC'' + ABC F3 = (A' + B' + C' + ') Enable 4:6 EC A'B'C'' A'B'C' 2 A'B'C' 3 A'B'C 4 A'BC'' 5 A'BC' 6 A'BC' 7 A'BC 8 AB'C'' 9 AB'C' AB'C' AB'C 2 ABC'' 3 ABC' 4 ABC' 5 ABC A B C

5 PLA implementation 5

6 ALU bitslice design ALU Operations -A (Two s complement of A) -B (Two s complement of B) A-B A+B 6

7 CE4: Components and esign Techniques for igital ystems Latches and flip-flops Tajana imunic osing ources: 7

8 implest circuits with feedback "remember" "data" "load" "stored value" 8

9 Flight attendant call button 3.2 Flight attendant call button Press call: light turns on tays on after button released Press cancel: light turns off Logic gate circuit to implement this? Call Cancel latch works Call= : sets to and keeps at Cancel= : resets to Call button Cancel button Bit torage Blue light. Call button pressed light turns on Call button Cancel button Bit torage Blue light 2. Call button released light stays on a a Call but ton Call button Cancel button Bit torage Blue light Cancel but ton Blue light 3. Cancel button pressed light turns off 9

10 What if a kid presses both call and cancel? Call but ton Blue light = = t Cancel but ton = = t = = t t If = and = at the same time and then released, =? Can also occur also due to different delays of different paths may oscillate and eventually settle to or due to diff. path delay

11 tate diagram Theoretical - latch state behavior states: possible values transitions: changes based on inputs Hard to observe in the - state one of or usually changes first non-deterministic transition to state - or -; a "race condition ; on = goes to either or ' = = possible oscillation between states and ' = = = = = = = ' ' = = = hold unstable = ' = = =

12 - latch analysis Break feedback path (t) ' (t+ ) (t) (t+ ) hold reset set X not allowed X (t) X X characteristic equation (t+ ) = + (t) 2

13 Oscillation solution: Level-ensitive Latch Add input C Change C to only after and are stable Level-sensitive latch C

14 Clocks Freq GHz GHz GHz MHz MHz Period. ns. ns ns ns ns Clock -- Pulsing signal for enabling latches; ticks like a clock ynchronous circuit: sequential circuit with a clock Clock period: time btwn pulse starts Above signal: period = 2 ns Clock cycle: one such time interval Above signal shows 3.5 clock cycles Clock duty cycle: time clock is high 5% in this case Clock frequency: /period Above : freq = / 2ns = 5MHz; 4

15 Level-ensitive Latch C C latch C latch requires careful design so = never occurs latch relieves designer of that burden Inserted inverter ensures always opposite of 5

16 Problem with Level-ensitive Latch Y C C2 C3 C4 Clk Clk_A Clk_B latch still has problem (as does latch) When C=, through how many latches will a signal travel? 6

17 Master-slave structure: Flip-Flop master stage slave stage P P CLK Break flow by alternating clocks (like an air-lock) use positive clock to latch inputs into one - latch use negative clock to change outputs with another - latch View pair as one basic unit output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops 7

18 Flip-Flop flip-flop Clk latch m m latch s s /m Cm Clk Cm master Cs s servant m/s Cs s Flip-flop: Bit storage that stores on clock edge, not level Master-slave design: o master loaded when C=, then slave when C= 8

19 Flip-Flop The triangle means clock input, edge triggered ymbol for rising-edge triggered flip-flop rising edges Clk ymbol for falling-edge triggered flip-flop Clk falling edges Internal design: Just invert servant clock rather than master 9

20 Flip-Flop Y Two latches inside each flip-flop Clk Clk_A Clk_B olves problem of not knowing through how many latches a signal travels when C= 2

21 Comparison of latches and flip-flops CLK positive edge-triggered flip-flop CLK edge G CLK latch transparent (level-sensitive) latch 2

22 Flip-Flop Types 3.5 flip-flop: like latch, but edge triggered JK flip-flop: like ( J, K) But when JK=, toggles, T flip-flop: JK with inputs tied together Toggles on every rising clock edge Previously utilized to minimize logic outside flip-flop Today, minimizing logic to such extent is not as important flip-flops are thus by far the most common 22

23 Flip-Flop et, eset and Active Hi/Low Inputs clk cycle cycle 2 cycle 3 cycle 4 A A A A ynchronous reset: clears to on next clock edge ynchronous set: sets to on next clock edge Asynchronous reset: clear to immediately - see diagram Asynchronous set: set to immediately 23

24 eset (set state to ) Flip-flop features synchronous: new = ' old (when next clock edge arrives) asynchronous: doesn't wait for clock Preset or set (set state to ) (or sometimes P) synchronous: new = old + (when next clock edge arrives) asynchronous: doesn't wait for clock Both reset and preset (set and reset dominant) new = ' old + (set-dominant) new = ' old + ' (reset-dominant) elective input capability (input enable or load) L or EN multiplexor at input: new = L' + L old load may or may not override reset/set (usually / have priority) Complementary outputs and ' 24

25 Negative edge-triggered flip-flop Efficient solution: only 6 gates sensitive to inputs only near edge of clock signal (not while high) holds when clock goes low characteristic equation (t+) = Clk= negative edge-triggered flip-flop (-FF) 4-5 gate delays holds when clock goes low must respect setup and hold time constraints to successfully capture input 25

26 Non-Ideal Flip-Flop Behavior clk C latch C u 2 setup time u clk 5 6 Can t change flip-flop input too close to clock edge etup time: time that must be stable before edge hold time Else, stable value not present at internal latch Hold time: time that must be held stable after edge Else, new value doesn t have time to loop around and stabilize in internal latch 26

27 Timing: efinitions data clock Clk T su.8 ns T h.5 ns T w 3.3 ns T su.8 ns T h.5 ns T w 3.3 ns T pd 3.6 ns. ns T pd 3.6 ns. ns etup time minimum time before the clocking event by which the input must be stable (Tsu) Hold time: minimum time after the clocking event until which the input must remain stable (Th) Propagation delay Amount of time for value to propagate from input to output (Tpd) 27

28 Bit torage Overview latch (set) (reset) Level-sensitive latch C C latch Clk latch mm Cm master flip-flop latch s s Cs s servant Feature: = sets to, = resets to. Problem: = yield undefined. Feature: and only have effect when C=. We can design outside circuit so = never happens when C=. Problem: avoiding = can be a burden. Feature: can t be if is stable before and while C=, and will be for only a brief glitch even if changes while C=. Problem: C= too long propagates new values through too many latches: too short may not enable a store. Feature: Only loads value present at rising clock edge, so values can t propagate to other flip-flops during same clock cycle. Tradeoff: uses more gates internally than latch, and requires more external gates than but gate count is less of an issue today. 28

29 Comparison of latches and flip-flops Type When inputs are sampled When output is valid unclocked always propagation delay from input change latch level-sensitive clock high propagation delay from input change latch (Tsu/Th around falling or clock edge (whichever is later) edge of clock) master-slave clock high propagation delay from falling edge flip-flop (Tsu/Th around falling of clock edge of clock) negative clock hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of clock flip-flop edge of clock) 29

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