Admin. ECE 550: Fundamentals of Computer Systems and Engineering. Last time. VHDL: Behavioral vs Structural. Memory Elements


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1 Admin C 55: Fundamentals of Computer ystems and ngineering torage and Clocking eading Finish up Chapter ecitation How is it going? VHL questions/issues? Homework Homework ubmissions vis akai C 55 (Hilton): torage and Clocking C 55 (Hilton): torage and Clocking 2 VHL: Behavioral vs tructural A few words about this tructural: pell out at (roughly) gate level Abstract piece into entities for abstraction/reuse Very easy to understand what synthesis does to it Behavioral: pell out at higher level equential statements, for loops, process blocks Can be difficult to understand how it synthesizes ifficult to resolve performance issues Last time Who can remind us what we did last time? C 55 (Hilton): torage and Clocking C 55 (Hilton): torage and Clocking 4 o far We can make logic to compute math Add, subtract, (we ll see multiply/divide later) Bitwise: AN, O, NOT, hifts election (MUX) pretty much anything But processors need state (hold value) egisters Memory lements All the circuits we looked at so far are combinational circuits: the output is a Boolean function of the inputs. We need circuits that can remember values. (registers) The output of the circuit is a function of the input AN a function of a stored value (state). Circuits with memory are called sequential circuits. Key to storage: loops from outputs to inputs C 55 (Hilton): torage and Clocking 5 C 55 (Hilton): torage and Clocking 6
2 NObased eteset () Latch eteset Latch (Continued)  on t set both & to C 55 (Hilton): torage and Clocking 7 C 55 (Hilton): torage and Clocking 8 eteset Latch (Continued) eteset Latch (Continued) et ignal Goes High et ignal Goes Low Output ignal Goes High C 55 (Hilton): torage and Clocking 9 Output ignal tays High C 55 (Hilton): torage and Clocking eteset Latch (Continued) Latch ownside: and at once = chaos ownside: Bad interface o let s build on it to do better Until eset ignal Goes High Then Output ignal Goes Low C 55 (Hilton): torage and Clocking C 55 (Hilton): torage and Clocking 2
3 ata Latch ( Latch) ata Latch ( Latch) nable ata We start with Latch We start with Latch..and add some gates at the front which change the interface ata + nable C 55 (Hilton): torage and Clocking C 55 (Hilton): torage and Clocking 4 ata Latch ( Latch) ata Latch ( Latch) nable  ata goes high nable  ata goes low oes not affect Output ed tays as output Output unchanged By changes to C 55 (Hilton): torage and Clocking 5 C 55 (Hilton): torage and Clocking 6 ata Latch ( Latch) ata Latch ( Latch) nable  ata goes high ed Becomes new output nable  ata light elay ( gates take time) C 55 (Hilton): torage and Clocking 7 C 55 (Hilton): torage and Clocking 8
4 Takes takes time: Gate delays: delay to switch each gate Wire delays: delay for signal to travel down wire Clocks Processors have a clock: Alternates Latch > logic > in one clock cycle Fan out: related to capacitance Need to make sure that signals timing is right on t want to have races or whacky conditions.. One clock cycle.4 GHz processor =.4 Billion clock cycles/sec C 55 (Hilton): torage and Clocking 9 C 55 (Hilton): torage and Clocking 2 trawman: Level Triggered First thoughts: Level Triggered Latch enabled when clock is high Hold value when clock is low trawman: Level Triggered Clock is low, all values stable C 55 (Hilton): torage and Clocking 2 C 55 (Hilton): torage and Clocking 22 trawman: Level Triggered Clock goes high, es capture and xmit new val trawman: Level Triggered ignals work their way through logic w/ high clk C 55 (Hilton): torage and Clocking 2 C 55 (Hilton): torage and Clocking 24
5 trawman: Level Triggered Clock goes low before signals reach next trawman: Level Triggered Clock goes low before signals reach next C 55 (Hilton): torage and Clocking 25 C 55 (Hilton): torage and Clocking 26 trawman: Level Triggered verything stable before clk goes high trawman: Level Triggered goes high again, repeat C 55 (Hilton): torage and Clocking 27 C 55 (Hilton): torage and Clocking 28 trawman: Level Triggered Problem: What if signal reaches too early? I.e., while clk is still high trawman: Level Triggered Problem: What if signal reaches too early? ignal goes right through, into next stage.. C 55 (Hilton): torage and Clocking 29 C 55 (Hilton): torage and Clocking
6 That would be bad Getting into a stage too early is bad omething else is going on there: corrupted Also may be a loop with one Consider incrementing counter Too fast: increment twice? eep dge Triggered Instead of level triggered Latch a new value at a level (high or low) We use edge triggered Latch a value at an edge (rising or falling) ising dges + C 55 (Hilton): torage and Clocking Falling dges C 55 (Hilton): torage and Clocking 2 FlipFlop FlipFlop C C ising edge triggered Flipflop Two Latches w/ Opposite clking of enables ising edge triggered Flipflop Two Latches w/ Opposite clking of enables On Low, first enabled (propagates value) econd not enabled, maintains value C 55 (Hilton): torage and Clocking C 55 (Hilton): torage and Clocking 4 FlipFlop FlipFlop C ising edge triggered Flipflop Two Latches w/ Opposite clking of enables On Low, first enabled (propagates value) econd not enabled, maintains value On High, second enabled First not enabled, maintains value No possibility of races anymore ven if I put 2 FFs backtoback By the time signal gets through 2 nd of st FF st of 2 nd FF is disabled till must ensure signals reach FF before clk rises Important concern in logic design making timing C 55 (Hilton): torage and Clocking 5 C 55 (Hilton): torage and Clocking 6
7 Making Timing Making timing is important in a design If you don t make timing, your logic won t compute right ynthesis tool (uartus) tells you what max freq unning above this your logic doesnt finish in time Flipflops (continued ) Could also do falling edge triggered witch which has NOT on clk Flipflop is ubiquitous Typically people just say and mean FF Which edge: doesn t matter As long as consistent in entire design We ll use rising edge C 55 (Hilton): torage and Clocking 7 C 55 (Hilton): torage and Clocking 8 flip flops Generally don t draw clk input Have one global clk, assume it goes there Often see > as symbol meaning clk Maybe have explicit enable Might not want to write every cycle If no enable signal shown, implies always enabled FF > FFs in VHL x: dffe port map ( clk => clk, d => someinput, q => theoutput, ena => en, the clock clrn => not(rst), clear prn => ''); the input is d the output is q the enable set FF FF Also, comes in dff with no enable Get output and NOT(output) for free C 55 (Hilton): torage and Clocking 9 C 55 (Hilton): torage and Clocking 4 A word of advice A few words about timing x_d signal x_q : std_logic; signal x_d: std_logic; x : dffe port map (, d=> x_d, q=>x_q, ); Use naming convention: x_d, x_q Write x_d, read x_q emember new value shows up next cycle x x_q Homework 2: VGA Controller equires certain clock frequency lse won t control monitor properly uartus will tell you what timing you make Fmax : how fast can this be clocked Tells you your worst timing paths From which dff to which dff Can see in schematic viewer (usually) Homework 2 hould be plenty of slack But if not C 55 (Hilton): torage and Clocking 4 C 55 (Hilton): torage and Clocking 42
8 Fixing timing misses Typical approach: reduce logic (gate delays) Better adder? ethink approach? Change don t care behavior? Fix high fanout uplicate high FO/simple logic Also, feel free to ask for help from me/tas uartus s tools to help you fix them aren t the best egister File Can store one value How about many? egister File In processor, holds values it computes on MIP, 2 2bit registers How do we build a egister File using FlipFlops? What other components do we need? C 55 (Hilton): torage and Clocking 4 C 55 (Hilton): torage and Clocking 44 egister File: Interface egister file strawman rnumw Wval rnuma egister File rnumb 4 inputs register numbers (5 bit): 2 read, write register write value (2 bits) 2 outputs 2 register values (2 bits) Aval Bval Use a mux to pick read? 2 input mux = slow (other regs not pictured) 2 bit reg 2 bit reg 2 bit reg 2 bit reg C 55 (Hilton): torage and Clocking 45 C 55 (Hilton): torage and Clocking 46 egister file strawman First: A ecoder Use a mux to pick read? 2 input mux = slow other regs not pictured Writing the registers Need to pick which reg Have reg num (e.g., 9) Need to make n9= n, n, = Wrata 2 bit reg n 2 bit reg n 2 bit reg n 2 bit reg n First task: convert binary number to one hot aw this before Take register number ecoder C 55 (Hilton): torage and Clocking 47 C 55 (Hilton): torage and Clocking 48
9 egister File Now we know how to write: Use decoder to convert reg # to one hot end write data to all regs Use one hot encoding of reg # to enable right reg till need to fix read side 2 input mux (the way we ve made it) not realistic To do this: expand our world from, to,, Z C 55 (Hilton): torage and Clocking 49 CMO: Complementary MO Vcc Output Gnd 2 inputs: and. What does this do? Output Write truth table for output C 55 (Hilton): torage and Clocking 5 CMO: Complementary MO Vcc CMO: Complementary MO Vcc Output Output Gnd Gnd 2 inputs: and. What does this do? Write truth table for output When =, straightforward Output C 55 (Hilton): torage and Clocking 5 2 inputs: and. What does this do? Write truth table for output When =, straightforward When =, no connection: Z Output Z Z C 55 (Hilton): torage and Clocking 52 High Impedance: Z Z = High Impedance No path to power or ground Gate does not produce a or a Previous slide: tristate inverter More commonly drawn: tristate buffer = enable, = data Out on t care Out X Z C 55 (Hilton): torage and Clocking 5 emember this rule? emember I told you not to connect two outputs? a b c d BA! If one gate tries to drive a and the other drives a One pumps water in.. The other sucks it out xcept its electric charge, not water hort circuit lots of current > lots of heat C 55 (Hilton): torage and Clocking 54
10 We ve had this rule one day... Its ok to connect multiple outputs together Under one circumstance (*): All but one must be outputting Z at any time (*) isclaimer: there are other circumstances but not doing them now C 55 (Hilton): torage and Clocking 55 Mux, implemented with tristates We can build effectively a mux from tristates Much more efficient for large #s of inputs (e.g., 2) 5 ecoder C 55 (Hilton): torage and Clocking 56 2 bit reg 2 bit reg 2 bit reg 2 bit reg Ports What we just saw: read port Ability to do one read / clock cycle Originally said want 2 reads: read 2 src registers /insn Maybe even more if we do many insns at once This design: can just put replicate Another decoder Another set of tristates Another output bus (wire connecting the tristates) arlier: write port Ability to do one write/cycle Could add more: need muxes to pick wr values Minor etail FYI: This is not how a register file is implemented (Though it is how other things are implemented) Actually done with AM We ll see how those work soon C 55 (Hilton): torage and Clocking 57 C 55 (Hilton): torage and Clocking 58 ummary Can layout logic to compute things Add, subtract, Now can store things flipflops egisters Also understand clocks C 55 (Hilton): torage and Clocking 59
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