Flip-Flops and Sequential Circuit Design

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1 Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6 JK Flip-Flop 7.7 Summary of Terminology 7.8 Registers 7.8. Shift Register Parallel-ccess Shift Register February 3, 22 ECE 52 - Digital Design Principles 2

2 Reading ssignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) 7.9 Counters 7.9. synchronous Counters Synchronous Counters Counters with Parallel Load 7. Reset Synchronization February 3, 22 ECE 52 - Digital Design Principles 3 Reading ssignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) 7. Other Types of Counters 7.. D Counter 7..2 Ring Counter 7..3 Johnson Counter 7..4 Remarks on Counter Design February 3, 22 ECE 52 - Digital Design Principles 4 2

3 Reading ssignment Brown and Vranesic (cont) 8 Synchronous Sequential Circuits 8. Basic Design Steps 8.. State Diagram 8..2 State Table 8..3 State ssignment 8..4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions 8..5 Timing Diagram 8..6 Summary of Design Steps February 3, 22 ECE 52 - Digital Design Principles 5 Reading ssignment Brown and Vranesic (cont) 8 Synchronous Sequential Circuits (cont) 8.2 State-ssignment Problem One-Hot Encoding 8.7 Design of a Counter Using the Sequential Circuit pproach 8.7. State Diagram and State Table for Modulo-8 Counter State ssignment Implementation Using D-Type Flip-Flops Implementation Using JK-Type Flip-Flops Example Different Counter February 3, 22 ECE 52 - Digital Design Principles 6 3

4 Reading ssignment Roth Latches and Flip-Flops.5 S-R Flip-Flop.6 J-K Flip-Flop.7 T Flip-Flop.8 Flip-Flops with dditional Inputs.9 Summary 2 Registers and Counters 2.5 Counter Design Using S-R and J-K Flip-Flops 2.6 Derivation of Flip-Flop Input Equations Summary February 3, 22 ECE 52 - Digital Design Principles 7 The JK Flip-Flop llows J = K = condition Implemented with a gated SR latch and feedback of Q and Q* Q toggles (Q + = Q ) on J = K = February 3, 22 ECE 52 - Digital Design Principles 8 4

5 The JK Flip-Flop (cont) Characteristic table and equation Karnaugh map of characteristic table Characteristic equation Q + = JQ + K Q February 3, 22 ECE 52 - Digital Design Principles 9 The JK Flip-Flop (cont) Implementation using a D flip-flop Characteristic Function at D input February 3, 22 ECE 52 - Digital Design Principles 5

6 The JK Flip-Flop State table NS (Q + ) PS (Q) JK = February 3, 22 ECE 52 - Digital Design Principles The JK Flip-Flop State diagram JK = JK = JK = JK = February 3, 22 ECE 52 - Digital Design Principles 2 6

7 The JK Flip-Flop With clock circuitry and timing Positive edge triggered JK flip-flop February 3, 22 ECE 52 - Digital Design Principles 3 The Master Slave JK Flip-Flop Master Slave JK Flip-Flop Rising edge triggered note CLK inverted to master February 3, 22 ECE 52 - Digital Design Principles 4 7

8 The Master Slave JK Flip-Flop Master Slave JK Flip-Flop Falling edge triggered note CLK (CP) inverted to slave February 3, 22 ECE 52 - Digital Design Principles 5 The Master Slave JK Flip-Flop Master active on CLK = Slave active on CLK = Latch data in master on CLK = Transfer data to slave (output) on CLK = Timing Diagram Initial Conditions CLK =, J =, K =, Y =, Q = February 3, 22 ECE 52 - Digital Design Principles 6 8

9 The Master Slave JK Flip-Flop Timing Diagram February 3, 22 ECE 52 - Digital Design Principles 7 The JK Flip-Flop (cont) What happens if J = K = for an indefinite period of time (i.e., much greater than clock period)? Output oscillates at ½ the frequency of the clock Divide by two counter February 3, 22 ECE 52 - Digital Design Principles 8 9

10 The T (Toggle or Trigger) Flip-Flop Connect J and K inputs together Combined input T Characteristic Table Characteristic Equation Timing Diagram February 3, 22 ECE 52 - Digital Design Principles 9 The T Flip-Flop State Table NS (Q + ) PS (Q) T = T= February 3, 22 ECE 52 - Digital Design Principles 2

11 The T Flip-Flop State Diagram T = T = T = T = February 3, 22 ECE 52 - Digital Design Principles 2 The T Flip-Flop (from JK/D) Q + = JQ + K Q Q + = T Q + TQ = T OR Q February 3, 22 ECE 52 - Digital Design Principles 22

12 Counter Design with T Flip-Flops 3 bit binary counter design example State refers to Q s of flip-flops 3 bits, 8 states Decimal through 7 No inputs Transition on every clock edge i.e., state changes on every clock edge ssume clocked, synchronous flip-flops February 3, 22 ECE 52 - Digital Design Principles 23 Counter Design with T Flip-Flops State Diagram February 3, 22 ECE 52 - Digital Design Principles 24 2

13 Counter Design with T Flip-Flops State table PS B C + NS B + C + February 3, 22 ECE 52 - Digital Design Principles 25 Counter Design with T Flip-Flops Next State Maps + = B + C + = D B + = B C + = D B C + = C = D C February 3, 22 ECE 52 - Digital Design Principles 26 3

14 Counter Design with T Flip-Flops Using D flip-flops, inputs are derived directly from next state maps D = Q + Using T flip flops Excitation table (used for design) T = Q OR Q + Need to find inputs to T flip-flops Mapping state changes Q Q+ requires T =? February 3, 22 ECE 52 - Digital Design Principles 27 Counter Design with T Flip-Flops T Flip-Flop Excitation Table T = Q OR Q + Q Q + T February 3, 22 ECE 52 - Digital Design Principles 28 4

15 Counter Design with T Flip-Flops State Variable T = + (OR) = + = T= = + = + = + = T= + = B + C + = D T = February 3, 22 ECE 52 - Digital Design Principles 29 Counter Design with T Flip-Flops State Variable B T B = B + (OR) B B= B= B + = B + = T= T= B + = B + = T= T= B + = B C + = D B T B = C February 3, 22 ECE 52 - Digital Design Principles 3 5

16 Counter Design with T Flip-Flops State Variable C T C = C + (OR) C C= C= C= C + = C + = T= T= T= T= C + = C + = T= T= T= T= C + = C = D C T C = February 3, 22 ECE 52 - Digital Design Principles 3 Counter Design with T Flip-Flops Implement design using T Flip-Flops with asynchronous preset and clear synchronous preset (PRN) and clear (CLRN) override clock and other inputs Preset : Q, Clear : Q Used to initialize system (all flip-flops) to known state Bubbles indicate low true or active low T =, TB = C, TC = February 3, 22 ECE 52 - Digital Design Principles 32 6

17 Counter Design with T Flip-Flops Schematic February 3, 22 ECE 52 - Digital Design Principles 33 Counter Design with T Flip-Flops Timing Diagram Q toggles when B = C = QB toggles when C = QC toggles on every clock edge February 3, 22 ECE 52 - Digital Design Principles 34 7

18 Counter Design with JK Flip-Flops State Diagram February 3, 22 ECE 52 - Digital Design Principles 35 Counter Design with JK Flip-Flops State Table PS B C + NS B + C + February 3, 22 ECE 52 - Digital Design Principles 36 8

19 Counter Design with JK Flip-Flops Next State Maps + = B = D B + = + = D B C + = B + = D C February 3, 22 ECE 52 - Digital Design Principles 37 Counter Design with JK Flip-Flops JK Flip-Flop Excitation Table Recall JK state diagram Create excitation table from state diagram Q + = JQ + K Q Q Q + JK = J JK = JK = K JK = February 3, 22 ECE 52 - Digital Design Principles 38 9

20 Counter Design with JK Flip-Flops State Variable + = B = + = + = = + = + = + = J = B K = B February 3, 22 ECE 52 - Digital Design Principles 39 Counter Design with JK Flip-Flops State Variable B B + = + B= B= J B = B + = B + = B + = B + = B + = B + = K B = C February 3, 22 ECE 52 - Digital Design Principles 4 2

21 Counter Design with JK Flip-Flops State Variable C C + = B + C= C= C= J C = + B C + = C + = C + = C + = C + = K C = February 3, 22 ECE 52 - Digital Design Principles 4 2

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