Sequential Circuits. Combinational Circuits Outputs depend on the current inputs

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1 Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating previous, current and future Called states or tokens Example: Finite State Machines (FSMs), Pipelines in CL out CL CL Finite State Machine Pipeline 1

2 Principles of VLSI esign Sequential Circuits Sequential Circuits If tokens moved through pipeline at constant speed, no sequencing elements will be needed Ex: Fibre-optic cable, called wave pipelining in circuits However, dispersion is high in most circuits We need to delay fast tokens, so that they don't catch up with slow tokens Use flip-flops to delay fast tokens so that they move through exactly one stage per cycle Inevitably adds some delay to slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Sometimes called clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 2

3 Principles of VLSI esign Sequential Circuits Sequential Elements Level sensitive Transparent latch latch Flip-Flop Edge triggered Master-slave flip-flop flip-flop, register Flop (latch) (flop) 3

4 Principles of VLSI esign Sequential Circuits Sequential Elements: Pass Transistor Pros: Tiny Low clock loads Cons: V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input 4

5 Principles of VLSI esign Sequential Circuits Sequential Elements: Transmission Gate No V t drop Requires inverted clock Inverting Buffer Pros: Restoring No backdriving Fixes either: output noise sensitivity Or diffusion input Cons: Inverted output X 5

6 Principles of VLSI esign Sequential Circuits Sequential Elements: Tristate feedback Static Backdriving risk Static latches are now essential X Buffered Input Fixes diffusion input Noninverting X 6

7 Principles of VLSI esign Sequential Circuits Sequential Elements: Buffered Output Non backdriving Widely used in standard cells Very robust (important feature) Rather large Rather slow (1.5-2 FO4 delays) High clock loading X atapath Smaller, faster Unbuffered input X 7

8 Principles of VLSI esign Sequential Circuits Sequential Elements: Flip-Flop Flip-Flop Built as a pair of back-to-back latches X X 8

9 Principles of VLSI esign Sequential Circuits Sequential Elements Enable Ignore clock when enable is inactive Mux: increase latch - delay Clock-gating: increase enable setup time, skew Symbol Multiplexer esign Clock Gating esign en 1 0 en en en Flop 1 0 en Flop Flop en 9

10 Principles of VLSI esign Sequential Circuits Sequential Elements Reset Force output low when reset is asserted Synchronous vs. asynchronous Symbol Flop reset reset Synchronous Reset Asynchronous Reset reset reset reset reset reset reset 10

11 Principles of VLSI esign Sequential Circuits Sequential Elements Set / Reset Set forces output high when asserted Flip-Flop with asynchronous set and reset set reset reset set 11

12 Principles of VLSI esign Sequential Circuits Timing iagrams A Combinational Logic Y A Y t cd t pd Contamination and propogation delays Flop t setup t hold t pcq t pd Logic Prop. elay t ccq t cd Logic Cont. elay t pcq t ccq t pdq t pcq t setup /Flop Clk- Prop elay /Flop Clk- Cont. elay - Prop elay - Cont. elay /Flop Setup Time t setup t hold t t ccq pcq t cdq t pdq t hold /Flop Hold Time 12

13 Principles of VLSI esign Sequential Circuits Sequencing Methods Flip-Flops T c Flip-Flops Flop Combinational Logic Flop 2-Phase latches Pulsed latches 2-Phase Transparent es Pulsed es 1 2 p t pw p T c /2 Combinational Logic t nonoverlap Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 t nonoverlap p 13

14 Principles of VLSI esign Sequential Circuits Max-elay: Flip-Flops T C = t pcq + t pd + t setup t pd T C ( t setup + t pcq ) sequencing delay F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 14

15 Principles of VLSI esign Sequential Circuits Max-elay: 2-Phase es T c t pdq1 + t pd1 + t pdq2 + t pd Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 t pd = t pd1 + t pd2 T c ( 2t pdq ) 1 sequencing delay 2 T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 15

16 Principles of VLSI esign Sequential Circuits Max-elay: Pulsed es T C max( t pdq + t pd, t pcq + t pd + t setup t pw ) t pd T C max( t pdq, t pcq + t setup t pw ) p p sequencing delay 1 L1 1 Combinational Logic 2 L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p t pcq tpd tsetup T c t pw 1 (b) t pw < t setup 2 16

17 Principles of VLSI esign Sequential Circuits Min-elay: Flip-Flops t cd t hold t ccq F1 1 CL 2 F2 1 t ccq t cd 2 t hold 17

18 Principles of VLSI esign Sequential Circuits Min-elay: 2 Phase es t cd1, t cd2 t hold t ccq t nonoverlap Hold time reduced by nonoverlap 1 2 L1 1 CL Paradox: Hold applies twice each cycle vs. only once for flops But flops have two latches!!! 2 L2 t nonoverlap 1 2 t ccq 1 t cd 2 t hold 18

19 Principles of VLSI esign Sequential Circuits Min-elay: Pulsed es t cd t hold t ccq + t pw Hold time increased by pulse width p L1 1 CL p 2 L2 p t pw t hold 1 t ccq t cd 2 19

20 Principles of VLSI esign Sequential Circuits Time Borrowing In a flip-flop based system ata launches on one rising/falling edge Must setup before next rising/falling edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system ata can pass through latch when transperent Long cycle of logic can borrow time into the next cycle As long as each loop completes in one cycle This mechanism is called time borrowing 20

21 Principles of VLSI esign Sequential Circuits Time Borrowing (a) Combinational Logic Combinational Logic Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Combinational Logic Combinational Logic Loops may borrow time internally but must complete within the cycle 21

22 Principles of VLSI esign Sequential Circuits Time Borrowing How much borrowing? 2 phased latches: pulsed latches: T C t borrow ( t 2 setup + t nonoverlap ) t borrow t pw t setup L1 1 Combinational Logic 1 2 L t nonoverlap T c T c /2 Nominal Half-Cycle 1 elay t borrow t setup 2 22

23 Principles of VLSI esign Sequential Circuits Clock Skew We have assumed zero clock skew F1 1 Combinational Logic 2 F2 Clock really have uncertainty in arrival time decrease max-delay increases min-delay decreases time borrowing 1 2 t pcq T c t pdq t setup t skew Clock Skew: Flip-flops F1 1 CL t pd T C ( t pcq t setup t skew ) 2 F2 t cd t hold t ccq + t skew t skew t hold 1 t ccq 2 t cd 23

24 Principles of VLSI esign Sequential Circuits Clock Skew: es Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 2 phased latches t pd T c ( 2t pdq ) 1 2 t cd1, t cd2 t hold t ccq t nonoverlap + t skew T C t borrow ( t 2 setup + t nonoverlap + t skew ) pulsed latches t pd T C max( t pdq, t pcq + t setup t pw + t skew ) t cd t hold t ccq + t pw + t skew t borrow t pw ( t setup + t skew ) 24

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