Sequential Circuit Design


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1 Sequential Circuit Design LanDa Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
2 Outlines Introduction Sequencing Methods Latches and FlipFlops Sequential System Design Conclusion LanDa Van VLSI062
3 Sequential Machines Use memory elements to make primary output values depend on (state + primary inputs). Varieties: Mealy machines outputs function of present state and inputs; Moore machines outputs depend only on state. Machine computes next state N, primary outputs O from current state S, primary inputs I. Nextstate function: N = δ(i,s). Output function (Mealy): O = λ(i,s). Duty cycle: fraction of clock period for which clock is active (e.g., for activelow clock, fraction of time clock is 0). LanDa Van VLSI063
4 FSM Structure LanDa Van VLSI064
5 Sequencing Elements Latch: level sensitive Transparent latch, D latch Flipflop: edge triggered Masterslave flipflop, D flipflop, D register Timing Diagrams Transparent Edgetrigger D clk Latch Q D clk Flop Q clk D Q (latch) Q (flop) LanDa Van VLSI065
6 Memory Elements Store a value as controlled by one or more control inputs. May have multiple control inputs. Clock, Load, SR, In CMOS, memory is created by: capacitance (dynamic); feedback (static). Storage element Latch: transparent when internal memory is being set from input. Flipflop: not transparent reading input and changing output are separate events. LanDa Van VLSI066
7 Memory Categories Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM LanDa Van VLSI067
8 Setup & Hold Times Setup time: time before clock during which data input must be stable. Hold time: time after clock event for which data input must remain stable. clock data LanDa Van VLSI068
9 Sequencing Methods Flipflops T c 2Phase Latches Pulsed Latches FlipFlops clk clk Flop Combinational Logic clk Flop 2Phase Transparent Latches Pulsed Latches φ 1 φ 2 φ p φ 1 φ 2 φ 1 Latch t pw φ p Latch T c /2 Combinational Logic t nonoverlap Latch Combinational Logic Combinational Logic HalfCycle 1 HalfCycle 1 t nonoverlap Latch φ p Latch LanDa Van VLSI069
10 Timing Diagrams Contamination and Propagation Delays t pd Logic Prop. Delay A Combinational Logic Y A Y t cd t pd t cd t pcq t ccq t pdq Logic Cont. Delay Latch/Flop ClkQ Prop Delay Latch/Flop ClkQ Cont. Delay Latch DQ Prop Delay D clk Flop Q clk D Q t setup t ccq t hold t pcq t pcq t setup t hold Latch DQ Cont. Delay Latch/Flop Setup Time Latch/Flop Hold Time D clk Latch Q clk D Q t setup t hold t t ccq pcq t cdq t pdq LanDa Van VLSI0610
11 MaxDelay: FlipFlops ( ) setup t T t + t pd c pcq sequencing overhead clk clk F1 Q1 Combinational Logic D2 F2 T c clk t pcq t setup Q1 t pd D2 LanDa Van VLSI0611
12 MaxDelay Example (1/2) Suppose the registers are built from flipflops with a setup time of 62ps, hold time of 10ps, propagation delay of 90nps and contamination delay of 75ps. LanDa Van VLSI0612
13 MaxDelay Example (2/2) T t + t + c pcq pd t setup t pd = = 1000 ps T c = 1152 ps LanDa Van VLSI0613
14 Max Delay: 2Phase Latches ( 2 ) tpd = tpd1+ tpd 2 Tc tpdq 123 sequencing overhead φ 1 φ 2 φ 1 D1 Q1 Combinational D2 Q2 Combinational D3 Logic 1 Logic 2 L1 L2 L3 Q3 φ 1 φ 2 T c D1 t pdq1 Q1 t pd1 D2 t pdq2 Q2 t pd2 D3 LanDa Van VLSI0614
15 Max Delay: Pulsed Latches ( ) setup tpd Tc max tpdq, tpcq + t tpw sequencing overhead L1 L2 LanDa Van VLSI0615
16 MaxDelay Example Recompute the ALU selfbypass path cycle time if the flipflop is replaced with a pulsed latch. The pulsed latch has a pulse width of 150 ps, a setup time of 40 ps, a hold time of 5 ps, a clktoq propagation delay of 82 ps and contamination delay of 52 ps, and a D toq propagation delay of 92 ps. Solution: t max (, ) pd Tc tpdq tpcq + tsetup tpw sequencing overhead T c max( , ) = 1092 ps LanDa Van VLSI0616
17 MinDelay: FlipFlops clk F1 Q1 CL t t t cd hold ccq clk D2 F2 clk Q1 t ccq t cd D2 t hold LanDa Van VLSI0617
18 MinDelay Example In the ALU selfbypass example with the flipflop from Fig. 7.6, the earliest input to the late bypass multiplexer is the imm value coming from another flipflop. Will this path experience any hold time failures? Solution: No. The late bypass mux has t cd =45 ps. The flipflops have t hold =10ps and t ccq =75 ps. Hence, t cd =45 ps is larger than (t hold t ccq =1075=85 ps). LanDa Van VLSI0618
19 D2 φ 1 φ 2 MinDelay: 2Phase Latches φ 2 L2 t t t t t cd1, cd 2 hold ccq nonoverlap t nonoverlap φ 1 L1 Q1 t ccq CL Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! Q1 t cd D2 t hold LanDa Van VLSI0619
20 MinDelay: Pulsed Latches t t t + t cd hold ccq pw φ p L1 φ p Q1 CL Hold time increased by pulse width D2 L2 φ p t pw t hold Q1 t ccq t cd D2 LanDa Van VLSI0620
21 Time Borrowing In a flopbased system: Data launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latchbased system Data can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle LanDa Van VLSI0621
22 Time Borrowing Example φ 1 φ 2 φ1 φ1 φ 2 (a) Latch Combinational Logic Latch Combinational Logic Latch Borrowing time across halfcycle boundary Borrowing time across pipeline stage boundary φ 1 φ 2 (b) Latch Combinational Logic Latch Combinational Logic Loops may borrow time internally but must complete within the cycle LanDa Van VLSI0622
23 2Phase Latches How Much Borrowing? T c borrow setup nonoverlap ( ) Pulsed Latches φ 1 φ 2 t t t t t + t borrow pw setup 2 D1 L1 Q1 Combinational Logic 1 D2 L2 Q2 φ 1 φ 2 t nonoverlap T c T c /2 Nominal HalfCycle 1 Delay t borrow t setup D2 LanDa Van VLSI0623
24 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time Decreases maximum propagation delay Increases minimum contamination delay Decreases time borrowing Clock must arrive at all memory elements in time to load data. LanDa Van VLSI0624
25 Clock Skew: FlipFlops F2 F1 F2 ( ) setup skew tpd Tc tpcq + t + t sequencing overhead F1 t t t + t cd hold ccq skew LanDa Van VLSI0625
26 Clock Skew: Latches 2Phase Latches ( 2 ) tpd Tc tpdq 123 sequencing overhead t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew φ 1 φ 2 φ 1 φ 2 φ 1 D1 Q1 Combinational D2 Q2 Combinational D3 Logic 1 Logic 2 L1 L2 L3 Q3 T t t + t + t 2 ( ) c borrow setup nonoverlap skew Pulsed Latches ( ) setup skew tpd Tc max tpdq, tpcq + t tpw + t sequencing overhead t t + t t + t cd hold pw ccq skew ( ) t t t + t borrow pw setup skew LanDa Van VLSI0626
27 TwoPhase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2 phase latches with big nonoverlap times Call these clocks φ 1, φ 2 (ph1, ph2) LanDa Van VLSI0627
28 Signal Skew Machine data signals must obey setup and hold times avoid signal skew. LanDa Van VLSI0628
29 Data Shoot Through Latches do not cut combinational logic when clock is active. Latchbased machines must use multiple ranks of latches. Multiple ranks require multiple phases of clock. Data shoot through occurs if singlephase latch is used. LanDa Van VLSI0629
30 Unbalanced Delays Logic with unbalanced delays leads to inefficient use of logic: short clock period long clock period LanDa Van VLSI0630
31 Retiming Solution Retiming moves memory elements through combinational logic: Property: Retiming changes encoding of values in registers, but proper values can be reconstructed with combinational logic. Retiming must preserve number of latches OR registers around a cycle. LanDa Van VLSI0631
32 Summary FlipFlops: Very easy to use, supported by all tools 2Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk LanDa Van VLSI0632
33 Outlines Introduction Sequential Methods Latches and FlipFlops Sequential System Design Conclusion LanDa Van VLSI0633
34 Dynamic Latch (1/3) Pass Transistor Latch Pros Tiny Low clock load Cons V t drop Leakage away Backdriving Diffusion input φ D Q Used in 1970 s Transmission gate No V t drop Leakage away Backdriving Diffusion input Requires inverted clock φ D Q φ LanDa Van VLSI0634
35 Dynamic Latch (2/3) Store charge on inverter gate capacitance: φ = 0: transmission gate is off, inverter output is determined by storage node. φ = 1: transmission gate is on, inverter output follows D input. LanDa Van VLSI0635
36 Dynamic Latch (3/3) Inverting buffer No V t drop Leakage away No backdriving Fixes either Diffusion input (upper side) Output noise sensitivity with inverted output (bottom side) Setup and hold times determined by transmission gate must ensure that value stored on transmission gate is solid. LanDa Van VLSI0636
37 Stick Diagram V DD D Q V SS φ φ LanDa Van VLSI0637
38 Physical Layout V DD D Q V SS φ φ LanDa Van VLSI0638
39 Multiplexer Dynamic Latch LanDa Van VLSI0639
40 Static Latch (1/3) Must use feedback to restore value. Some latches are static on one phase (pseudostatic) load on one phase, activate feedback on other phase. SR Latch LanDa Van VLSI0640
41 Static Latch (2/3) Tristate feedback φ No V t drop Leakage compensation D X Q Backdriving risk Diffusion input φ φ Nonisolated from output noise Requires inverted clock Buffered input No V t drop φ φ Leakage compensation No backdriving No diffusion input D φ X φ Q Nonisolated from output noise Requires inverted clock φ LanDa Van VLSI0641
42 Static Latch (3/3) Buffered output No V t drop Leakage compensation No backdriving No diffusion input Isolated from output noise Requires inverted clock Widely used in Artisan standard cells Very robust (most important) Rather large Rather slow (1.5 2 FO4 delays) High clock loading D φ φ X φ φ Q LanDa Van VLSI0642
43 Multiplexer Static Latches Mux Static Latch No V t drop Leakage compensation No backdriving No diffusion input Requires inverted clock Negative Latch Positive Latch LanDa Van VLSI0643
44 Recirculating QuasiStatic Latch Eliminate the problem: the value stored on the capacitor leaks away over time on dynamic latch Quasistatic: the latch data will vanish if the clocks are ceased. (i.e. static on one phase) LanDa Van VLSI0644
45 Clocked Inverter φ = 0: If both clocked transistors are off, output is floating. φ = 1: If both clocked inverters are on, acts as an inverter to drive output. circuit symbol LanDa Van VLSI0645
46 Clocked Inverter Latch φ = 0: i1 is off, i2i3 form feedback circuit. φ = 1: i2 is off, breaking feedback; i1 is on, driving i3 and output. Static Latch is transparent when φ = 1. LanDa Van VLSI0646
47 FlipFlops Not transparent use multiple storage elements to isolate output from input. EdgeTrigger: masterslave LanDa Van VLSI0647
48 MasterSlave FlipFlop φ = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so pop the output of the master. φ = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value. master slave D Q φ LanDa Van VLSI0648
49 LatchBased FlipFlop The storage nodes have to be refreshed at periodic intervals LanDa Van VLSI0649
50 Resettable Latches and FlipFlop LanDa Van VLSI0650
51 Static LatchBased FlipFlop: Clock Skew Problem DLatch DLatch The 11 clock overlap introduces a race condition. During the 11 overlap, node A is driven by both D and B. LanDa Van VLSI0651
52 Outlines Introduction Sequencing Methods Latches and FlipFlops Sequential System Design Conclusion LanDa Van VLSI0652
53 Sequential Machine Design Procedure Step1: Specification Step2: Formulation Obtain a state diagram or state table Step3: State Assignment Obtain state table if only a state diagram is available previously and assign binary codes to the states Step4: FlipFlop Input Equation Determination Select flipflop types and derive flipflop equations from next state entries in the table Step5: Output Equation Determination Derive output equations from output entries in the table Step6: Optimization Optimize the equations Step7: Technology Mapping Find circuit from equations and map to flipflops and gate Step8: Verification Verify correctness of final design LanDa Van VLSI0653
54 State Transition Graphs/Tables Basic functional description of FSM. Symbolic truth table for nextstate, output functions: no structure of logic; no encoding of states. State transition graph and table are functionally equivalent. LanDa Van VLSI0654
55 State Assignment Must find binary encoding for symbolic states state assignment. State assignment affects: combinational logic area; combinational logic delay; memory element area. May also encode some machine inputs/outputs. LanDa Van VLSI0655
56 Example: Onebit Counter (1/4) Easy to specify as onebit counter. Harder to specify nbit counter behavior. Can specify nbit counter as structure made of 1bit counters. State table: Count Cin Next Count Cout (Carry Out) LanDa Van VLSI0656
57 Onebit Counter Implementation (2/4) XOR computes next value of this bit of counter. NAND/inverter computes carryout. LanDa Van VLSI0657
58 Onebit Counter Sticks Diagram (3/4) C out V DD l1(latch) n(nand) i(inv) x(xor) l2(latch) φ 1 φ 1 φ 2 φ 2 C in V SS LanDa Van VLSI0658
59 nbit Counter Structure (4/4) LanDa Van VLSI0659
60 Example: 01 String Recognizer (1/5) LanDa Van VLSI Behavior of machine which recognizes 01 in continuous stream of bits. Operation: Waits for 0 to appear in state bit1. Goes into separate state bit2 when 0 appears. If 1 appears immediately after 0, can t have a 01 on next cycle, so can go back to wait for 0 in state bit1. Time Input State Bit1 Bit2 Bit2 Bit1 Bit1 Bit2 Next Bit2 Bit2 Bit1 Bit1 Bit2 Bit1 Output
61 State Transition Table (2/5) Operation: Waits for 0 to appear in state bit1. Goes into separate state bit2 when 0 appears. If 1 appears immediately after 0, can t have a 01 on next cycle, so can go back to wait for 0 in state bit1. Input Present Next Output 0 Bit1 Bit2 0 1 Bit1 Bit1 0 0 Bit2 Bit2 0 1 Bit2 Bit1 1 LanDa Van VLSI0661
62 State Transition Graph (3/5) Equivalent to state transition table: LanDa Van VLSI0662
63 01 Recognizer Encoding (4/5) Choose bit1=0, bit2=1, and then truth table is as follows: Input Present Next Output LanDa Van VLSI0663
64 01 Recognizer Logic Implementation (5/5) After encoding, truth table can be implemented in gates: Q D Q D LanDa Van VLSI0664
65 Power Optimization Memory elements stop glitch propagation: Glitch LanDa Van VLSI0665
66 Conclusions You should learn in depth about the following topics: Latch FlipFlop Sequencing Sequential Circuits Sequential system clock discipline LanDa Van VLSI0666
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