FlipFlops and Sequential Circuit Design. ECE 152A Winter 2012


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1 FlipFlops and Sequential Circuit Design ECE 52 Winter 22
2 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6 JK FlipFlop 7.7 Summary of Terminology 7.8 Registers 7.8. Shift Register Parallelccess Shift Register February 3, 22 ECE 52  Digital Design Principles 2
3 Reading ssignment Brown and Vranesic (cont) 7 FlipFlops, Registers, Counters and a Simple Processor (cont) 7.9 Counters 7.9. synchronous Counters Synchronous Counters Counters with Parallel Load 7. Reset Synchronization February 3, 22 ECE 52  Digital Design Principles 3
4 Reading ssignment Brown and Vranesic (cont) 7 FlipFlops, Registers, Counters and a Simple Processor (cont) 7. Other Types of Counters 7.. D Counter 7..2 Ring Counter 7..3 Johnson Counter 7..4 Remarks on Counter Design February 3, 22 ECE 52  Digital Design Principles 4
5 Reading ssignment Brown and Vranesic (cont) 8 Synchronous Sequential Circuits 8. Basic Design Steps 8.. State Diagram 8..2 State Table 8..3 State ssignment 8..4 Choice of FlipFlops and Derivation of NextState and Output Expressions 8..5 Timing Diagram 8..6 Summary of Design Steps February 3, 22 ECE 52  Digital Design Principles 5
6 Reading ssignment Brown and Vranesic (cont) 8 Synchronous Sequential Circuits (cont) 8.2 Statessignment Problem OneHot Encoding 8.7 Design of a Counter Using the Sequential Circuit pproach 8.7. State Diagram and State Table for Modulo8 Counter State ssignment Implementation Using DType FlipFlops Implementation Using JKType FlipFlops Example Different Counter February 3, 22 ECE 52  Digital Design Principles 6
7 Reading ssignment Roth Latches and FlipFlops.5 SR FlipFlop.6 JK FlipFlop.7 T FlipFlop.8 FlipFlops with dditional Inputs.9 Summary 2 Registers and Counters 2.5 Counter Design Using SR and JK FlipFlops 2.6 Derivation of FlipFlop Input Equations Summary February 3, 22 ECE 52  Digital Design Principles 7
8 The JK FlipFlop llows J = K = condition Implemented with a gated SR latch and feedback of Q and Q* Q toggles (Q + = Q ) on J = K = February 3, 22 ECE 52  Digital Design Principles 8
9 The JK FlipFlop (cont) Characteristic table and equation Karnaugh map of characteristic table Characteristic equation Q + = JQ + K Q February 3, 22 ECE 52  Digital Design Principles 9
10 The JK FlipFlop (cont) Implementation using a D flipflop Characteristic Function at D input February 3, 22 ECE 52  Digital Design Principles
11 The JK FlipFlop State table NS (Q + ) PS (Q) JK = February 3, 22 ECE 52  Digital Design Principles
12 The JK FlipFlop State diagram JK = JK = JK = JK = February 3, 22 ECE 52  Digital Design Principles 2
13 The JK FlipFlop With clock circuitry and timing Positive edge triggered JK flipflop February 3, 22 ECE 52  Digital Design Principles 3
14 The Master Slave JK FlipFlop Master Slave JK FlipFlop Rising edge triggered note CLK inverted to master February 3, 22 ECE 52  Digital Design Principles 4
15 The Master Slave JK FlipFlop Master Slave JK FlipFlop Falling edge triggered note CLK (CP) inverted to slave February 3, 22 ECE 52  Digital Design Principles 5
16 The Master Slave JK FlipFlop Master active on CLK = Slave active on CLK = Latch data in master on CLK = Transfer data to slave (output) on CLK = Timing Diagram Initial Conditions CLK =, J =, K =, Y =, Q = February 3, 22 ECE 52  Digital Design Principles 6
17 The Master Slave JK FlipFlop Timing Diagram February 3, 22 ECE 52  Digital Design Principles 7
18 The JK FlipFlop (cont) What happens if J = K = for an indefinite period of time (i.e., much greater than clock period)? Output oscillates at ½ the frequency of the clock Divide by two counter February 3, 22 ECE 52  Digital Design Principles 8
19 The T (Toggle or Trigger) FlipFlop Connect J and K inputs together Combined input T Characteristic Table Characteristic Equation Timing Diagram February 3, 22 ECE 52  Digital Design Principles 9
20 The T FlipFlop State Table PS (Q) NS (Q + ) T = T= February 3, 22 ECE 52  Digital Design Principles 2
21 The T FlipFlop State Diagram T = T = T = T = February 3, 22 ECE 52  Digital Design Principles 2
22 The T FlipFlop (from JK/D) Q + = JQ + K Q Q + = T Q + TQ = T OR Q February 3, 22 ECE 52  Digital Design Principles 22
23 Counter Design with T FlipFlops 3 bit binary counter design example State refers to Q s of flipflops 3 bits, 8 states Decimal through 7 No inputs Transition on every clock edge i.e., state changes on every clock edge ssume clocked, synchronous flipflops February 3, 22 ECE 52  Digital Design Principles 23
24 Counter Design with T FlipFlops State Diagram February 3, 22 ECE 52  Digital Design Principles 24
25 February 3, 22 ECE 52  Digital Design Principles 25 Counter Design with T FlipFlops State table C + B + + C B NS PS
26 Counter Design with T FlipFlops Next State Maps + = B + C + = D B + = B C + = D B C + = C = D C February 3, 22 ECE 52  Digital Design Principles 26
27 Counter Design with T FlipFlops Using D flipflops, inputs are derived directly from next state maps D = Q + Using T flip flops Excitation table (used for design) T = Q OR Q + Need to find inputs to T flipflops Mapping state changes Q Q+ requires T =? February 3, 22 ECE 52  Digital Design Principles 27
28 Counter Design with T FlipFlops T FlipFlop Excitation Table T = Q OR Q + Q Q + T February 3, 22 ECE 52  Digital Design Principles 28
29 Counter Design with T FlipFlops State Variable T = + (OR) = + = T= = + = + = + = T= + = B + C + = D T = February 3, 22 ECE 52  Digital Design Principles 29
30 Counter Design with T FlipFlops State Variable B T B = B + (OR) B B= B= B + = B + = T= T= B + = B + = T= T= B + = B C + = D B T B = C February 3, 22 ECE 52  Digital Design Principles 3
31 Counter Design with T FlipFlops State Variable C T C = C + (OR) C C= C= C= C + = C + = T= T= T= T= C + = C + = T= T= T= T= C + = C = D C T C = February 3, 22 ECE 52  Digital Design Principles 3
32 Counter Design with T FlipFlops Implement design using T FlipFlops with asynchronous preset and clear synchronous preset (PRN) and clear (CLRN) override clock and other inputs Preset : Q, Clear : Q Used to initialize system (all flipflops) to known state Bubbles indicate low true or active low T =, TB = C, TC = February 3, 22 ECE 52  Digital Design Principles 32
33 Counter Design with T FlipFlops Schematic February 3, 22 ECE 52  Digital Design Principles 33
34 Counter Design with T FlipFlops Timing Diagram Q toggles when B = C = QB toggles when C = QC toggles on every clock edge February 3, 22 ECE 52  Digital Design Principles 34
35 Counter Design with JK FlipFlops State Diagram February 3, 22 ECE 52  Digital Design Principles 35
36 February 3, 22 ECE 52  Digital Design Principles 36 Counter Design with JK FlipFlops State Table C + B + + C B NS PS
37 Counter Design with JK FlipFlops Next State Maps + = B = D B + = + = D B C + = B + = D C February 3, 22 ECE 52  Digital Design Principles 37
38 Counter Design with JK FlipFlops JK FlipFlop Excitation Table Recall JK state diagram Create excitation table from state diagram Q + = JQ + K Q Q Q + JK = J JK = JK = K JK = February 3, 22 ECE 52  Digital Design Principles 38
39 Counter Design with JK FlipFlops State Variable + = B = + = + = = + = + = + = J = B K = B February 3, 22 ECE 52  Digital Design Principles 39
40 Counter Design with JK FlipFlops State Variable B B + = + B= B= J B = B + = B + = B + = B + = B + = B + = K B = C February 3, 22 ECE 52  Digital Design Principles 4
41 Counter Design with JK FlipFlops State Variable C C + = B + C= C= C= J C = + B C + = C + = C + = C + = C + = K C = February 3, 22 ECE 52  Digital Design Principles 4
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