Engr354: Digital Logic Circuits

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1 Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops; State diagrams; esign techniques for circuits that use flip-flops. Engr354 - Chapter 7, Brown

2 Circuit Types Combinational output depends only on the input. Sequential output depends on input and past behavior. Requires use of storage elements. Contents of the storage elements is called state. Circuit goes through a sequence of states as a result of changes in inputs. Synchronous controlled by a clock. Clock Signals Engr354 - Chapter 7, Brown 2

3 A Bistable Memory Element Bistable possessing two stable states. A B A / (SR) Memory Element Most often called a Basic Cell. NOR centered Basic Cell Circuit (a), Function table (b). are active when they are high. Blocking side inputs. Engr354 - Chapter 7, Brown 3

4 Typical Operation of a Basic Cell, clear., preset. NOR-Centered ( ominant) Basic Cell r + s Circuit r sr Action n+ hold n reset set reset Operation Table n n+ φ φ φ φ r State iagram Engr354 - Chapter 7, Brown 4

5 NAN-Centered ( ominant) Basic Cell are active low. Operation table indicates assertion, not voltage, levels. s Circuit rs s Action N+ hold N reset set set Operation Table n n+ φ φ φ φ s + r State iagram Combined Form of the Basic Cell n n+ φ φ φ φ NAN-centered n n+ n n+ φ φ φ φ NOR-centered φ φ Combined Form Basic Cell Engr354 - Chapter 7, Brown 5

6 esigning Latches - A Model Latch - a logic circuit that transfers the input state to the output state when the clock signal is high, and latches and holds the value of the input at the output when the clock signal goes low. n n+ φ φ Combined Form Clock S R Basic Cell (H) (L) esign of a Clocked (ata) Latch Clock S R Basic Cell (H) (L) Engr354 - Chapter 7, Brown 6

7 esign of a Clocked Latch (H) Action N+ x hold reset set Block iagram N Operation Table n n+ φ φ Basic Cell n n+ φ φ φ φ φ φ Truth Table = clk = clk Equations CLK + CLK +CLK CLK State iagram Clocked Latch Engr354 - Chapter 7, Brown 7

8 esign of a Clocked Toggle (T) Latch (H) T T Action N+ x Hold N Hold N Toggle N Function Table Block iagram n n+ φ φ Basic Cell T n n+ φ φ φ φ φ φ Truth Table = clk T = clk T Equations T CLK T + CLK T +CLK T CLK State iagram esign of a Clocked JK Latch (H) J K J K Action N+ x x Hold N Hold N Toggle N Function Table Block iagram n n+ φ φ Basic Cell = clk J = clk K Equations J K n n+ φ φ φ φ φ φ φ φ φ φ φ φ Truth Table Engr354 - Chapter 7, Brown 8

9 esign of a -ominant Clocked SR Latch S R Clock S R Basic Cell (H) (L) S, R, Clock, Outputs, esign of a -ominant Clocked SR Latch (H) S R Action N+ hold N reset set set Operation Table Block iagram n n+ φ φ Basic Cell = clk S = clk R S Equations n n+ φ φ φ φ φ φ φ φ φ φ φ φ φ Truth Table Engr354 - Chapter 7, Brown 9

10 SR Latch with Enable (Clock) esign of a Clocked JK Latch Version II Replace the basic cell with a -latch as the memory element. J K -Latch (H) (L) J, K,, Output Engr354 - Chapter 7, Brown

11 esign of a Clocked JK Latch Version II (H) J K J K Action N+ x x Hold N Hold N Toggle N Function Table Block iagram n n+ Truth Table = K + clk + clk J Equation J K n n+ Terminology Latches are often called Transparent because the output will follow the inputs as long as the clock signal is high. Flip-flops are edge-triggered. Positive-edge triggered (PET) is when action occurs on the rising edge of the clock signal. Negative-edge triggered (NET) is when action occurs on the falling edge of the clock signal. Types of Flip-flops SR (rarely used). (very, very common, 74HC74). JK (hardly ever used, 74HC9). Toggle (occasionally used by CA programs). Engr354 - Chapter 7, Brown

12 up and Hold Times up time (t SU ) is the time interval preceding the active transition point of the CLK during which all data inputs must remain stable. Hold time (t H ) is the time interval following the active transition point of the CLK during which all data inputs must remain stable. See data sheet for 74HC74 t su t h PET Master-Slave Flip-Flop M follows the input whenever CLK is low. When CLK goes high, M is transferred to the output. Engr354 - Chapter 7, Brown 2

13 Positive-Edge-Triggered Flip-Flop PET Flip-Flop with Clear and Preset Synchronous transitions or actions occur in relation to the CLK signal. Asynchronous transitions or actions are not related to the CLK signal. Engr354 - Chapter 7, Brown 3

14 Level-Sensitive vs. Edge Triggered Level-sensitive = latch Edge-triggered = flip-flop a Clock a b Clock b a c b c c (a) Circuit (b) Timing diagram esign a T Flip-Flop from a Flip-Flop Note that the memory element is now edge-triggered. Note that the signal is no longer part of the next-state logic. T flip-flop (H) (L) T ( n + ) ( n) ( n) Function Table n n+ T n n+ Truth Table Engr354 - Chapter 7, Brown 4

15 esign a T Flip-Flop from a Flip-Flop T Clock (a) Circuit T (c) Graphical symbol esign a JK Flip-Flop from a Flip-Flop Clock J K Circuit J K ( n+ ) ( n) ( n) Function Table J K Graphical symbol Engr354 - Chapter 7, Brown 5

16 Summary of Terminology Basic cell cross-coupled NAN/NOR. Gated latch output may change when clk =. Gated SR latch. Gated latch. Gated JK latch. Flip-flop output changes only on edge. Master-slave. Edge-triggered. Three main types. (very, very common, 74HC74). JK (hardly ever used, 74HC9). Toggle (occasionally used by CA programs). Sequential Elements Summary In this chapter you learned about: circuits that can store information; Basic cells, latches, and flip-flops; State diagrams; esign techniques for circuits that use flip-flops. Engr354 - Chapter 7, Brown 6

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