Engr354: Digital Logic Circuits


 Sabina Sparks
 2 years ago
 Views:
Transcription
1 Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flipflops; State diagrams; esign techniques for circuits that use flipflops. Engr354  Chapter 7, Brown
2 Circuit Types Combinational output depends only on the input. Sequential output depends on input and past behavior. Requires use of storage elements. Contents of the storage elements is called state. Circuit goes through a sequence of states as a result of changes in inputs. Synchronous controlled by a clock. Clock Signals Engr354  Chapter 7, Brown 2
3 A Bistable Memory Element Bistable possessing two stable states. A B A / (SR) Memory Element Most often called a Basic Cell. NOR centered Basic Cell Circuit (a), Function table (b). are active when they are high. Blocking side inputs. Engr354  Chapter 7, Brown 3
4 Typical Operation of a Basic Cell, clear., preset. NORCentered ( ominant) Basic Cell r + s Circuit r sr Action n+ hold n reset set reset Operation Table n n+ φ φ φ φ r State iagram Engr354  Chapter 7, Brown 4
5 NANCentered ( ominant) Basic Cell are active low. Operation table indicates assertion, not voltage, levels. s Circuit rs s Action N+ hold N reset set set Operation Table n n+ φ φ φ φ s + r State iagram Combined Form of the Basic Cell n n+ φ φ φ φ NANcentered n n+ n n+ φ φ φ φ NORcentered φ φ Combined Form Basic Cell Engr354  Chapter 7, Brown 5
6 esigning Latches  A Model Latch  a logic circuit that transfers the input state to the output state when the clock signal is high, and latches and holds the value of the input at the output when the clock signal goes low. n n+ φ φ Combined Form Clock S R Basic Cell (H) (L) esign of a Clocked (ata) Latch Clock S R Basic Cell (H) (L) Engr354  Chapter 7, Brown 6
7 esign of a Clocked Latch (H) Action N+ x hold reset set Block iagram N Operation Table n n+ φ φ Basic Cell n n+ φ φ φ φ φ φ Truth Table = clk = clk Equations CLK + CLK +CLK CLK State iagram Clocked Latch Engr354  Chapter 7, Brown 7
8 esign of a Clocked Toggle (T) Latch (H) T T Action N+ x Hold N Hold N Toggle N Function Table Block iagram n n+ φ φ Basic Cell T n n+ φ φ φ φ φ φ Truth Table = clk T = clk T Equations T CLK T + CLK T +CLK T CLK State iagram esign of a Clocked JK Latch (H) J K J K Action N+ x x Hold N Hold N Toggle N Function Table Block iagram n n+ φ φ Basic Cell = clk J = clk K Equations J K n n+ φ φ φ φ φ φ φ φ φ φ φ φ Truth Table Engr354  Chapter 7, Brown 8
9 esign of a ominant Clocked SR Latch S R Clock S R Basic Cell (H) (L) S, R, Clock, Outputs, esign of a ominant Clocked SR Latch (H) S R Action N+ hold N reset set set Operation Table Block iagram n n+ φ φ Basic Cell = clk S = clk R S Equations n n+ φ φ φ φ φ φ φ φ φ φ φ φ φ Truth Table Engr354  Chapter 7, Brown 9
10 SR Latch with Enable (Clock) esign of a Clocked JK Latch Version II Replace the basic cell with a latch as the memory element. J K Latch (H) (L) J, K,, Output Engr354  Chapter 7, Brown
11 esign of a Clocked JK Latch Version II (H) J K J K Action N+ x x Hold N Hold N Toggle N Function Table Block iagram n n+ Truth Table = K + clk + clk J Equation J K n n+ Terminology Latches are often called Transparent because the output will follow the inputs as long as the clock signal is high. Flipflops are edgetriggered. Positiveedge triggered (PET) is when action occurs on the rising edge of the clock signal. Negativeedge triggered (NET) is when action occurs on the falling edge of the clock signal. Types of Flipflops SR (rarely used). (very, very common, 74HC74). JK (hardly ever used, 74HC9). Toggle (occasionally used by CA programs). Engr354  Chapter 7, Brown
12 up and Hold Times up time (t SU ) is the time interval preceding the active transition point of the CLK during which all data inputs must remain stable. Hold time (t H ) is the time interval following the active transition point of the CLK during which all data inputs must remain stable. See data sheet for 74HC74 t su t h PET MasterSlave FlipFlop M follows the input whenever CLK is low. When CLK goes high, M is transferred to the output. Engr354  Chapter 7, Brown 2
13 PositiveEdgeTriggered FlipFlop PET FlipFlop with Clear and Preset Synchronous transitions or actions occur in relation to the CLK signal. Asynchronous transitions or actions are not related to the CLK signal. Engr354  Chapter 7, Brown 3
14 LevelSensitive vs. Edge Triggered Levelsensitive = latch Edgetriggered = flipflop a Clock a b Clock b a c b c c (a) Circuit (b) Timing diagram esign a T FlipFlop from a FlipFlop Note that the memory element is now edgetriggered. Note that the signal is no longer part of the nextstate logic. T flipflop (H) (L) T ( n + ) ( n) ( n) Function Table n n+ T n n+ Truth Table Engr354  Chapter 7, Brown 4
15 esign a T FlipFlop from a FlipFlop T Clock (a) Circuit T (c) Graphical symbol esign a JK FlipFlop from a FlipFlop Clock J K Circuit J K ( n+ ) ( n) ( n) Function Table J K Graphical symbol Engr354  Chapter 7, Brown 5
16 Summary of Terminology Basic cell crosscoupled NAN/NOR. Gated latch output may change when clk =. Gated SR latch. Gated latch. Gated JK latch. Flipflop output changes only on edge. Masterslave. Edgetriggered. Three main types. (very, very common, 74HC74). JK (hardly ever used, 74HC9). Toggle (occasionally used by CA programs). Sequential Elements Summary In this chapter you learned about: circuits that can store information; Basic cells, latches, and flipflops; State diagrams; esign techniques for circuits that use flipflops. Engr354  Chapter 7, Brown 6
ECE380 Digital Logic
ECE38 igital Logic FlipFlops, Registers and Counters: FlipFlops r.. J. Jackson Lecture 25 Flipflops The gated latch circuits presented are level sensitive and can change states more than once during
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More informationECE 301 Digital Electronics
ECE 301 Digital Electronics Latches and FlipFlops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and
More informationCHAPTER 11 LATCHES AND FLIPFLOPS
CHAPTER 11 LATCHES AND FLIPFLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 SetReset Latch 11.3 Gated D Latch 11.4 EdgeTriggered D FlipFlop 11.5 SR FlipFlop
More informationL4: Sequential Building Blocks (Flipflops, Latches and Registers)
L4: Sequential Building Blocks (Flipflops, Latches and Registers) (Most) Lecture material derived from R. Katz, Contemporary Logic esign, Addison Wesley Publishing Company, Reading, MA, 993. Some material
More informationLecture 10. Latches and FlipFlops
Logic Design Lecture. Latches and FlipFlops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly
More informationCombinational circuit Memory elements. Fig. 51 Block Diagram of Sequential Circuit Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Inputs ombinational circuit Memory elements Outputs Fig. 5 Block Diagram of Sequential ircuit 22 Prentice Hall, Inc. Inputs ombinational circuit Outputs Flipflops lock pulses (a) Block diagram (b) Timing
More informationLecture 9: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 9: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationL4: Sequential Building Blocks (Flipflops, Latches and Registers)
L4: Sequential Building Blocks (Flipflops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
More informationBasic bistable element. Chapter 6. Latches vs. flipflops. Flipflops
Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. FlipFlops and Simple FlipFlop Applications.. Huang, 24 igital Logic esign
More informationCS 226: Digital Logic Design
CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 44 Objectives In this lecture we will introduce: 1. Synchronous
More informationUnit 3 Combinational MOS Logic Circuits
Unit 3 ombinational MOS Logic ircuits LATH Latch It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationAn astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator can be used as a pulse generator.
Concepts In sequential logic, the outputs depend not only on the inputs, but also on the preceding input values... it has memory. Memory can be implemented in 2 ways: Positive feedback or regeneration
More information14:332:231 DIGITAL LOGIC DESIGN. D Latch
4:332:23 IGIAL LOGI ESIGN Ivan Marsic, Rutgers University Electrical & omputer Engineering Fall 23 Lecture #6: Latch ; FlipFlops Latch ata latch: single input, plus enable input he Latch eliminates the
More informationUnit 4 Session  15 FlipFlops
Objectives Unit 4 Session  15 FlipFlops Usage of D flipflop IC Show the truth table for the edgetriggered D flipflop and edgetriggered JK flipflop Discuss some of the timing problems related to
More informationCSE 271 Introduction to Digital Systems Supplementary Reading Some Basic Memory Elements
CE 27 Introduction to igital ystems upplementary eading ome Basic Memory Elements In this supplementary reading, we will show some some basic memory elements. In particular, we will pay attention to their
More informationChapter 14 Sequential logic, Latches and FlipFlops
Chapter 14 Sequential logic, Latches and FlipFlops Flops Lesson 6  Flip Flop and Latch Ch14L6"igital Principles and esign", Raj Kamal, Pearson Education, 2006 2  FlipFlop + ve edge triggered Output
More informationSynchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic 5 Outline! Sequential Circuits! Latches! FlipFlops! Analysis of Clocked Sequential Circuits! State Reduction and Assignment! Design Procedure 52 Sequential Circuits!
More informationENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine
More informationChapter 5 Latch and flipflop
257 Chapter 5 Latch and flipflop «from the ground up I2013b  Copyright Daniele Giacomini  appunti2@gmail.com http://a3.informaticalibera.net 5.1 Propagation delay..................................
More informationSequential Circuits: Latches and FlipFlops
Sequential Circuits: Latches and FlipFlops Sequential circuits Output depends on current input and past sequence of input(s) How can we tell if the input is current or from the past? A clock pulse can
More informationSequential Circuits: Latches & FlipFlops
Sequential Circuits: Latches & FlipFlops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc
More informationFigure 3. Ball and hill analogy for metastable behavior. S' R' Q Q next Q next ' 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 0 (a)
Chapter 5 Latches and FlipFlops Page 1 of 17 5. Latches and FlipFlops Latches and flipflops are the basic elements for storing information. One latch or flipflop can store one bit of information. The
More informationLecture 8: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 8: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationFigure 2.1(a) Bistable element circuit.
3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationSequential Circuits: Latches & FlipFlops
ESD I Lecture 3.b Sequential Circuits: Latches & FlipFlops 1 Outline Memory elements Latch SR latch D latch FlipFlop SR flipflop D flipflop JK flipflop T flipflop 2 Introduction A sequential circuit
More informationCDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch EdgeTriggered D FlipFlop (FF) SR FlipFlop (FF) JK FlipFlop (FF) T FlipFlop
More informationDIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flipflops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC
More informationSynchronous Sequential Logic. Logic and Digital System Design  CS 303 Erkay Savaş Sabanci University
Synchronous Sequential Logic Logic and Digital System Design  S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs
More information7. Latches and FlipFlops
Chapter 7 Latches and FlipFlops Page 1 of 18 7. Latches and FlipFlops Latches and flipflops are the basic elements for storing information. One latch or flipflop can store one bit of information. The
More informationSwitching Circuits & Logic Design
witching Circuits & Logic esign JieHong oland Jiang 江介宏 epartment of Electrical Engineering National Taiwan University Fall 23 Latches and FlipFlops http://www3.niaid.nih.gov/topics/malaria/lifecycle.htm
More informationTheory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
More informationIn Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current
Module 12 In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current inputs. The following topics will be on sequential
More informationConstruct a truth table for this circuit. Write Boolean expressions for X and Q.
A olution X Construct a truth table for this circuit. X X Write Boolean expressions for X and. X = (+)'; = (+X)' = ' X' = ' (+) Let = =. Then = (+) = 3 The previous circuit is called an Latch and is usually
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationSequential Logic Design Principles.Latches and FlipFlops
Sequential Logic Design Principles.Latches and FlipFlops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and FlipFlops SR Latch
More informationModule3 SEQUENTIAL LOGIC CIRCUITS
Module3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.
More informationChapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
More informationChapter 5. FlipFlops, Registers, and Counters
Chapter 5 FlipFlops, Registers, and Counters Sensor Reset Set Memory element On Off Alarm Figure 5.1. Control of an alarm system. A B Figure 5.2. A simple memory element. Reset Set Figure 5.3. A memory
More information3 FlipFlops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.
3 FlipFlops Flipflops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory
More informationClocks. Sequential Logic. A clock is a freerunning signal with a cycle time.
Clocks A clock is a freerunning signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high
More information7. Sequential Circuits  Combinational vs. Sequential Circuits  7. Sequential Circuits  State (2)  7. Sequential Circuits  State (1) 
Sistemas Digitais I LESI  2º ano Lesson 7  Sequential Systems Principles Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática  Combinational vs. Sequential Circuits  Logic circuits are
More informationSequential Circuits. Chapter 4 S. Dandamudi
Sequential Circuits Chapter 4 S. Dandamudi Outline Introduction Clock signal Propagation delay Latches SR latch Clocked SR latch D latch JK latch Flip flops D flip flop JK flip flop Example chips Example
More informationContents. Chapter 6 Latches and FlipFlops Page 1 of 27
Chapter 6 Latches and FlipFlops Page 1 of 27 Contents Latches and FlipFlops...2 6.1 Bistable lement...3 6.2 SR Latch...4 6.3 SR Latch with nable...6 6.4 Latch...7 6.5 Latch with nable...8 6.6 Clock...9
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationLatches and FlipFlops
Latches and FlipFlops Introduction to sequential logic Latches SR Latch Gated SR Latch Gated Latch FlipFlops JK Flipflop Flipflop T Flipflop JK MasterSlave Flipflop Preset and Clear functions 7474
More informationFlipFlops and Sequential Circuit Design. ECE 152A Winter 2012
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationFlipFlops and Sequential Circuit Design
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationECE 331 Digital System Design
ECE 331 Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #21) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,
More informationECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo
ECE 223 Digital Circuits and Systems Synchronous Logic M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo Sequential Circuits Combinational circuits Output = f (present inputs)
More informationCHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS This chapter in the book includes: Objectives Study Guide 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State
More informationTo design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
More informationSetReset (SR) Latch
eteset () Latch Asynchronous Level sensitive crosscoupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0? 0? Indeterminate crosscoupled Nand gates
More informationSAMPLE OF THE STUDY MATERIAL PART OF CHAPTER 5. Combinational & Sequential Circuits
SAMPLE OF THE STUD MATERIAL PART OF CHAPTER 5 5. Introduction Digital circuits can be classified into two types: Combinational digital circuits and Sequential digital circuits. 5.2 Combinational Digital
More informationMaster/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
More informationOutputs Combinational circuit. Next state
4 Figure 4 lock iagram of a Sequential ircuit Inputs Outputs ombinational circuit Next state Storage elements Present state 2 Prentice Hall, Inc. 42 Figure 42 Logic Structures for Storing Information
More informationChapter 14 Sequential logic, Latches and FlipFlops
Chapter 14 Sequential logic, Latches and FlipFlops Flops Lesson 2 Sequential logic circuit, Flip Flop and Latch Introduction Ch14L2"Digital Principles and Design", Raj Kamal, Pearson Education, 2006
More informationChapter 9 Latches, FlipFlops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, FlipFlops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationChapter 5 Bistable memory devices. Copyright The McGrawHill Companies, Inc. Permission required for reproduction or display.
Chapter 5 Bistable memory devices Copyright The McGrawHill Companies, Inc. Permission required for reproduction or display. Digital circuits Combinational Sequential Logic gates Decoders, MUXes, Adders,
More informationSequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More information5. Sequential CMOS Logic Circuits
5. Sequential CMOS Logic Circuits In sequential logic circuits the output signals is determined by the current inputs as well as the previously applied input variables. Fig. 5.1a shows a sequential circuit
More informationCSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap 5, App. A& B) Number representations Boolean algebra OP and PO Logic
More informationLecture 22: Sequential Circuits. Sequential Circuits. Characteristic Table, SR Latch. SR Latch (Clocked) Latches:
Lecture 22: Sequential Circuits Latches: SR D JK FlipFlops Memory Sequential Circuits In sequential circuits, new state depends on not only the input, but also on the previous state. Devices like registers
More informationChapter 3 :: Sequential Logic Design
Chapter 3 :: Sequential Logic Design Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 3 Bistable Circuit Fundamental building block of other state
More informationEEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #6: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 extended, same due date as Lab 4 HW4 issued today Amirtharajah/Parkhurst,
More informationMaster/Slave Flip Flops
MSFF Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch (master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the
More informationSequential Logic Latches & Flipflops
Sequential Logic Latches & Flipflops Introduction Memory Elements PulseTriggered Latch SR Latch Gated SR Latch Gated D Latch EdgeTriggered Flipflops SR Flipflop D Flipflop JK Flipflop T Flipflop
More informationEE 110 Practice Problems for Final Exam: Solutions
EE 1 Practice Problems for Final Exam: Solutions 1. Finite State Machines: Sequence Recognizer You want to build a finite state machine that will recognize the sequence x = and output the sequence z =
More information1. A Sequential Parity Checker
Chapter 13: Analysis of Clocked Sequential Circuits 1. A Sequential Parity Checker When binary data is transmitted or stored, an extra bit (called a parity bit) is frequently added for purposes of error
More informationDesign of Digital Systems II Sequential Logic Design Principles (1)
Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic
More informationD FlipFlop Example (continued)
D FlipFlop Example Design a sequential circuit with one D flipflop, two inputs and, and external gates. The circuit operation is specified by the following table: 0 0 1 1 0 1 0 1 Operation Q (next clock
More informationET398 LAB 6. FlipFlops in VHDL
ET398 LAB 6 FlipFlops in VHDL FlipFlops March 3, 2013 Tiffany Turner OBJECTIVE The objectives of this lab are for you to begin the sequential and memory programming using flip flops in VHDL program.
More informationPage 2 CK K. Figure 3: JK Flipflops with asynchronous PRESET and CLEAR inpu CK K. Figure 2: JK Flipflops with different types of triggering
EGR 78 Digital Logic Lab File: N78L9A Lab # 9 Multivibrators A. Objective The objective of this laboratory is to introduce the student to the use of bistable multivibrators (flipflops), monostable multivibrators
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIPFLOPS
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIPFLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential
More informationChapter  5 FLIPFLOPS AND SIMPLE FLIPFLOP APPLICATIONS
Chapter  5 FLIPFLOPS AND SIMPLE FLIPFLOP APPLICATIONS Introduction : Logic circuit is divided into two types. 1. Combinational Logic Circuit 2. Sequential Logic Circuit Definition : 1. Combinational
More informationECE380 Digital Logic
ECE38 Digital Logic FlipFlops, egisters and Counters: Latches Dr. D. J. Jackson Lecture 24 torage elements Previously, we have considered combinational circuits where the output values depend only on
More informationSequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
More informationLatches and Flipflops
Latches and Flipflops Latches and flipflops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0
More informationCounter/shiftregister model. State machine model (cont d) General state machine model
CSE 37 Spring 26 Introduction to igital esign Lecture 8: Moore and Mealy Machines Last Lecture Finite State Machines Today Moore and Mealy Machines Counter/shiftregister model Values stored in registers
More informationCombinational and Sequential Circuits.
Combinational and Sequential Circuits. Basically, sequential circuits have memory and combinational circuits do not. Here is a basic depiction of a sequential circuit. All sequential circuits contain combinational
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationSequential Logic Design Principles.Clocked Synchronous StateMachine Analysis and Synthesis
Sequential Logic Design Principles.Clocked Synchronous StateMachine Analysis and Synthesis Doru Todinca Department of Computers Politehnica University of Timisoara Outline Clocked Synchronous StateMachine
More informationLecture 11: Sequential Circuit Design
Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Minelay Clock Skew Time Borrowing TwoPhase Clocking 2 Sequencing Combinational logic output depends on current
More informationKarnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.
Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0
More informationSEQUENTIAL CIRCUITS. Block diagram. Flip Flop. SR Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
More informationSequential Logic. References:
Sequential Logic References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian,
More informationFigure 7.1. Control of an alarm system. Figure 7.2. A simple memory element. Figure 7.3. A controlled memory element.
Sensor Set Memory element On Off Alarm A B Figure 7.. Control of an alarm system. Figure 7.2. A simple memory element. Load ata G A B Output Set G2 Figure 7.3. A controlled memory element. Figure 7.4.
More informationOverview. Ripple Counter Synchronous Binary Counters
Counters Overview Ripple Counter Synchronous Binary Counters Design with D FlipFlops Design with JK FlipFlops Serial Vs. Parallel Counters Updown Binary Counter Binary Counter with Parallel Load BCD
More informationChapter 5 Synchronous Sequential Logic 51 Sequential Circuits
Chapter 5 Synchronous Sequential Logic 51 Sequential Circuits Every digital system is likely to have combinational circuits, most systems encountered in practice also include storage elements, which require
More informationLecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Minelay
More informationSlides for Lecture 23
Slides for Lecture 23 ENEL 353: Digital Circuits Fall 213 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 1 November, 213 ENEL 353 F13
More informationUNIVERSITI MALAYSIA PERLIS DKT DIGITAL SYSTEMS II. Lab 1 : Flip Flops
UNIVERSITI MALAYSIA PERLIS DKT 212/3 : DIGITAL SYSTEM II Lab 1 : Flip Flops Name : Matrix No. : Program : Date : LAB 1: FLIPFLOPS OBJECTIVES 1. To construct the basic circuit of latches and flipflops
More informationSequential Logic. SR Latch
n 2/24/3 Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the
More informationCHAPTER TEN. 10.1 New Truth Table Symbols. 10.1.1 Edges/Transitions. Memory Cells
CHAPTER TEN Memory Cells The previous chapters presented the concepts and tools behind processing binary data. This is only half of the battle though. For example, a logic circuit uses inputs to calculate
More informationModeling Sequential Elements with Verilog. Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 41 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More information