# 2 : BISTABLES. In this Chapter, you will find out about bistables which are the fundamental building blocks of electronic counting circuits.

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1 2 : BITABLE In this Chapter, you will find out about bistables which are the fundamental building blos of electronic counting circuits. et-reset bistable A bistable circuit, also called a latch, or flip-flop, has two stable states. The output of a bistable can be either logic 1, or logic 0, according to signals received at its inputs. One of the simplest bistable circuits consists of two NAN gates: ET NAN EET NAN As you can see, there are two inputs, the ET and EET. The bars over these symbols indicate that these inputs are active LOW. In other words, each input must be held HIGH and pulsed LOW when you want something to happen. and are the outputs of the circuit and normally have opposite logic states. The bistable is ET when =1 and =0, and EET when =0 and =1. This kind of bistable is called a set-reset bistable, bistable, or sometimes bistable, latch or flip-flop, and is often represented by a simplified symbol, as follows: _ ymbol for an bistable A practical circuit for a NAN gate bistable needs switches to provide logic signals. ince the ET and EET inputs are to be held HIGH and pulsed LOW, you need switches with pull up resistors, as indicated in the circuit diagram which follows: Electronic Clos PAGE 2.1

2 +9 V 10 kω pull up resistors NAN ET EET NAN 0 V It would be useful to monitor the and outputs with LEs which illuminate when each output is HIGH: 10 kω pull up resistors NAN +9 V 680 Ω NAN ET EET NAN 0 V NAN emember that the outputs of the NAN gates driving the LEs do not produce valid logic signals. As you can see, the whole circuit requires four NAN gates and can therefore be assembled using a single 4011 CMO integrated circuit. The prototype board layout for this is shown at the top of 2.1. Go ahead and build the circuit, following the layout carefully. Look at the way in which the push button switches are connected on the prototype board. The placement of the link wires to the inputs of the 4011 NAN gates exploits the way in which the contacts are PAGE 2.2 iscovering

3

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5 arranged inside the switch. As you can see in the diagram below, the top two pins of the switch are internally connected by a metal strip: minature tactile switch metal strip inside switch contacts bridged by pressing button The bottom two pins are internally connected in the same way. As a result, either pin from each pair can be used to make connections to other parts of the circuit. This is a common arrangement for push button switches intended for use on printed circuit boards, PCBs, and helps to simplify the design of PCB layouts for keyboard circuits. An important new component has been added to the prototype board layout. This is the 47 µf decoupling capacitor connected across the power supply from +9 V to 0 V. Why is it there? The answer is that the decoupling capacitor prevents the transfer of rapid or transient signals, or glitches, from one part of the circuit to another along the power supply connections. CMO i.c. s are relatively vulnerable to this sort of interference and the addition of 47 µf, or 100 µf decoupling capacitors, connected as close to the power supply pins of individual integrated circuits as possible, is recommended. ometimes, you will see a decoupling arrangement like this: + V 47 µf nf 0 V This arrangement looks strange because the values of capacitors connected in parallel add together: Ctotal = C1 + C2... Here C total = = µ F. ince the tolerance of a 47 µf capacitor is likely to be as much as 20%, it seems pointless to add such a small capacitor in parallel. In fact, the behaviour of practical polarized and non-polarized capacitors is different, with nonpolarised capacitors working more effectively for high frequency signals. Think about decoupling capacitors as part of the recipe for getting CMO circuits to work and don t forget to put them in. Test your set-reset bistable. What happens when you operate the ET push button? What happens when you operate the EET push button? What happens when you operate both buttons at once? Electronic Clos PAGE 2.3

6 In this last condition, both and LEs should illuminate. This is often described as a disallowed state. The bistable isn t damaged, but it is impossible to predict which output will remain HIGH when the buttons are released. A set-reset bistable is often used as a memory device, for example in a burglar alarm, which remains ON once it has been triggered. A different application for a set-reset bistable is in debouncing a switch. The metal contacts inside a switch are springy and often bounce when the switch state is altered. Contacts may close, not once, but several times. With an oscilloscope, to monitor voltage/time changes, this is what you might see at the inputs and outputs of the bistable: 'ON' bounces 'OFF' bounces ET switch switch pressed V t EET switch switch pressed output rising edge EBOUNCE OUTPUT PULE falling edge Although, the signals at the ET and EET inputs change many times, the output changes just once from LOW to HIGH, and once from HIGH to LOW. In this way, you can produce a debounced output pulse. Pressing the ET switch gives a rising edge, pressing the EET switch gives a falling edge. -type bistable For electronic counting, a more sophisticated type of bistable is needed. The diagram at the top of the next page shows the connections for a -type bistable. As you can see, there are four different inputs: The ATA input is held at logic 1 or logic 0 and can be changed from one logic state to the other at any time. The small triangle inside the symbol indicates that the CLOCK input is edge-triggered. This is an important property. The CLOCK input of a -type bistable responds only to rising edges, PAGE 2.4 iscovering

7 that is, a rapid change from LOW to HIGH. low changes and sustained HIGH or LOW signals have no effect. The and inputs are the ET and EET. The absence of bars above these inputs indicates that they are active HIGH. In other words, and should be held LOW and pulsed HIGH to ET or EET the bistable. and are the outputs as before: ATA input CLOCK input ymbol for a -type bistable To describe the action of a -type bistable, you can say that the logic state at the -input is transferred to the -output on the rising edge of the clo. This statement is easier to understand once you have built and tested a prototype circuit. This is shown on the lower half of 2.1, and uses a new CMO integrated circuit, the In fact, a 4013 contains two separate -type bistables with pin connections as follows: type bistables V 2 3 -type 1 -type V 7 8 For the present, you are going to use the -type bistable connected to pins 1-6, leaving the other bistable unconnected. (In any final circuit, all unused CMO inputs must be connected either to +9 V or Electronic Clos PAGE 2.5

8 0 V, but you can usually work on prototype board without worrying about the unused parts of the integrated circuit.) Build the -type circuit, following 2.1 carefully. Connect the power supply and the CLOCK input from the first prototype board as shown, then investigate the action of the -type: Verify the action of the -type ET and EET switches. Whenever these switches are pressed, the output of the -type will change accordingly. The ET and EET inputs are levelsensitive, rather than edge-triggered. What happens if the ET and EET are pressed simultaneously? This is a disallowed state, as with the NAN gate bistable. Press the EET switch to force =0, then connect the ATA input to +9 V, using a flying lead from the prototype board, see 2.1. Press the EET switch on the NAN gate circuit (first prototype board) and then press the ET switch on the NAN gate circuit. This produces a rising edge at the CLOCK input of the -type bistable, provided you have connected the two prototype boards together. At the exact moment that the rising edge occurs, the -output of the -type bistable will go HIGH. isconnect the flying lead from +9 V. Because of the pull down resistor, the ATA input immediately returns to LOW. oes this have any effect on the outputs of the -type? epeat the EET/ET sequence with the NAN gate circuit. Again, the output of the -type changes at the exact moment that the rising edge arrives. This is what is meant by edge-triggered behaviour. Continue to investigate the -type until you are confident that you understand what each of the inputs and outputs will do. tart counting... on t take your carefully assembled prototype board circuits to bits. You will need them both for the practical work described in this section. Electronic counting depends on toggle bistables. This isn t an entirely new variety of bistable you have to learn about but is easily made by connecting the -output of a -type bistable to its ATA input, as shown in the diagram which follows: PAGE 2.6 iscovering

9 pulses OUT pulses IN A toggle bistable The special property of a toggle bistable is that its output changes state every time an input pulse arrives. You can convert your -type bistable circuit to a toggle bistable by removing one link and inserting another. o this now, following the layout at the top of 2.2. There is a new link from to the ATA input and the connection to the second LE has been removed. Keep the connections with the NAN gate bistable prototype circuit. EET the NAN gate bistable and then press ET and EET in sequence in order to deliver a series of input pulses to the CLOCK input of the toggle bistable. The output of the toggle bistable changes state for each input pulse received. trictly, for each rising edge received. With an oscilloscope, the changes observed are like this: NAN gate bistable switches ET EET INPUT pulses -OUTPUT pulses V As you can see, the -output changes at the beginning of each input pulse. You should be able to see this happen when you press the NAN gate bistable ET button. Count the input pulses in the diagram above. Answer: 4 Count the output pulses in the diagram above. Answer: 2 The toggle bistable divides the number of input pulses by two. This is really the same as counting the input pulses. To make this clear, you t Electronic Clos PAGE 2.7

10 can now add a second toggle bistable to the first, as shown in the layout at the bottom of 2.2. Add the links following the layout carefully. Your circuit is now: pulses OUT pulses IN TOGGLE BITABLE (ET and EET inputs connected to 0 V through pull down resistors) 680 Ω 1 +9 V 680 Ω INICATO kω kω 2 The output of the first -type is a pulse waveform with rising edges and these trigger the second bistable as follows: 0 V NAN gate bistable switches ET EET V INPUT pulses t 1-OUTPUT pulses 2-OUTPUT pulses You have added a second divide-by-two circuit, with one 2-output pulse for every four input pulses. It is helpful to convert these waveforms into truth table format, with each line in the truth table corresponding to one of the numbered arrows at the bottom of the diagram: PAGE 2.8 iscovering

11 pulse number 2 output 1 output repeated sequence In the table, the 1 output is on the right because it is the least significant bit, LB, of a binary number. The counting sequence for the circuit is , in descending binary order. You have built a 2-bit binary down counter. There are 2 -types and 2 2 =4 different output states. How could you make a 3-bit binary down counter? Easy! add another toggle bistable: OUTPUT pulses IN 0 V 3-bit binary down counter How may output states would this have. The calculation is 2 3 =8 output states. For a 4-bit counter (2 4 =16 output states) you would add a fourth bistable, and so on. This is all very well, but how can you make an up counter, which is likely to be more useful for counting in general and for electronic clo circuits in particular? This is easier than it sounds. All you need to do is to rearrange the connections between the toggle bistables. Instead of connecting the -output to the CLOCK input of the next Electronic Clos PAGE 2.9

12 stage, the -output is connected to the CLOCK input of the next stage. The circuit becomes: pulses IN to next stage TOGGLE BITABLE (ET and EET inputs connected to 0 V through pull down resistors) 47 kω 680 Ω 1 47 kω +9 V 680 Ω 2 INICATO 0 V Che ba with the layout at the bottom of 2.2, and make this modification. The waveforms at the counter outputs are changed to: NAN gate bistable switches ET EET V INPUT pulses t 1-OUTPUT pulses 2-OUTPUT pulses The truth table for the counter outputs is changed as well and the outputs now follow the repeated sequence , that is, binary numbers in ascending order: PAGE 2.10 iscovering

13 pulse number 2 output 1 output repeated sequence Notice again, that the 1-output appears in the table at the right hand side because it is the LB of the binary number. Confirm the behaviour of your counter by sending pulses to the CLOCK input from the NAN gate bistable, as before. Here is the circuit for a 3-bit binary up counter: OUTPUT pulses IN to next stage 0 V 3-bit binary up counter To make a 4-bit binary up counter, you add a fourth toggle bistable connected in the same way, and so on. To summarise: OWN counter: to CLOCK input of next stage UP counter: to CLOCK input of next stage Electronic Clos PAGE 2.11

14 What s next? You will find out more about counters in due course. The counters described in this Chapter count only in powers of two, 2 2 =4, 2 3 =8, 2 4 =16 and so on. How can you make a decimal counter, which counts in 10 s? How could you link counters together to count up to 60, to count seconds or minutes, or to 12 or 24 for hours? imilarly, how can you process the outputs of counters to give a user-friendly display? All of these questions have answers and, as you work through the next few Chapters, you will find out what they are. PAGE 2.12 iscovering

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