Registers & Counters


 Rudolph Golden
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1 Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multibit storage devices. Introduce counters by adding logic to registers implementing the functional capability to increment and/or decrement their contents. Define shift registers and show how they can be used to implement counters that use the onehot code. Reading Assignment Sections 4.4 and 5.4. Registers A register is a memory device that can be used to store more than one bit of information. A register is usually realized as several flipflops with common control signals that control the movement of data to and from the register. Common refers to the property that the control signals apply to all flipflops in the same way A register is a generalization of a flipflop. Where a flipflop stores one bit, a register stores several bits The main operations on a register are the same as for any storage devices, namely Load or Store: Put new data into the register Read: Retrieve the data stored in the register (usually without changing the stored data 2
2 Control Signals When they are asserted, they initiate an action in the register Asynchronous Control Signals cause the action to take place immediately Synchronous Control Signals must be asserted during a clock assertion to have an effect Examples On the following three registers, which control signals are asynchronous and which are synchronous? How are the control signals asserted? 3 D D D D module reg (STO,, D, ); parameter n = 6; input STO, ; input [n:] D; output [n:] ; reg [n:] ; STO or negedge ) if ( ==) <= ; else <= D; D n D n STO endmodule 4 2
3 D K D K D n n LD CLK OE K 5 D D D D D D n n LD CLK OE 6 3
4 Verilog description of previous two registers module reg2 (CLK,, LD, OE, D, ); parameter n = 4; input CLK,, LD, OE; input [n:] D; output [n:] ; reg [n:] I, ; integer k; CLK) if () I <= ; else if (LD) I <= D; if (OE) = I; else = 'bz; endmodule 7 2. Counters A counter is a register capable of incrementing and/or decrementing its contents plus n minus n The definition of "plus" and "minus" depend on the way the register contents encode the integers Binary Counters: Encode the integers with the binary number code 8 4
5 Example: 3bit binary counter: plus minus Count Sequence Transistion Table State Table What does the counter count? The output signals are just the state variables 9 Example: 3bit binary up/down counter TransistionTable Example: Binary mod 6 counter x x x x x x Transistion Table State Diagram 5
6 Design of a Binary Up Counter i toggles on every clock cycle where j =, for i > j K K K K Binary Up Counter 2 6
7 Design of a Binary Down Counter i toggles on every clock cycle where j =, for i > j 3 Binary Down Counter 4 7
8 Synchronous, SeriesCarry Binary Counter 2 3 K K K K = K K2 =4 =5 = T W 3 2 t PFF t PG K3 t PG t su T W t PFF + (n2)t PG + t su (for n 2) 5 Synchronous, ParallelCarry Binary Counter 2 3 K K K K =4 =5 = 3 2 = K K2 t PFF t PG T W K3 t PG t su T W t PFF + t PG + t su (for n 3) 6 8
9 Asynchronous Counters K K K K Typical MSI counter chip 74LS63 LD ENP ENT A B C D A B C D RCO LD and are synchronous LD asserted during the rising edge of the clock loads the register from ABCD. asserted during the rising edge of the clock clears the counter overrides LD LD overrides EN R CO = D C B A ENT, used for cascading chips 7 Verilog description of the 74x63 module V74x63 (CLK, _L, LD_L, ENP, ENT, D,, RCO); input CLK, _L, LD_L, ENP, ENT; input [3:] D; output RCO; output [3:] ; reg [3:] ; reg RCO; CLK) if (_L == ) <= 4'b; else if (LD_L == ) <= D; else if (ENT & ENP) <= +; or ENT) if ( == 5 && ENT == ) RCO = ; else RCO = ; endmodule 8 9
10 Verilog description of an up/down counter module updowncount (R, Clock, L, E, up_down, ); parameter n = 8; input [n:] R; input Clock, L, E, up_down; output [n:] ; reg [n:] ; integer direction; Clock) begin if (up_down) direction = ; else direction = ; if (L) <= R; else if (E) <=  + direction; end endmodule 9 Verilog description of modn counters module upmodn (Ck, ); parameter n = 6; input Ck; output [3:] ; reg [3:] ; Ck) if ( == n) <= ; else <= + ; endmodule module dwnmodn (Ck, ); parameter n = 5; input Ck; output [3:] ; reg [3:] ; Ck) if ( == ) <= n; else <= ; endmodule 2
11 Design of Mod n Counters Mod 6 Up Counter 2 / CLK 74LS63 LD ENP ENT A B C D A B C D RCO Mod 5 Down Counter 2 /LD CLK 74LS69 U/D LD ENP ENT A B C D A B C D RCO 2 Decoding Binary Counter States A B C A B C Y Y Y2 Y3 Y4 Y5 Y6 Y7 /S /S /S2 /S3 /S4 /S5 /S6 /S7 2 /S /S /S2 The decoding spikes are hazzards that can not be designed out The following circuit will mask the decoding spikes, at the cost of delaying the outputs one clock cycle. A B C A B C Y Y Y2 Y3 Y4 Y5 Y6 Y7 REG CLK 22
12 3. Shift Registers How would you add a control signal to control when the shift register shifted? How would you add parallel input capability and why would you want to? What kind of control signals are needed? Is the shift register drawn above a left shifter or a right shifter? How would you make a shift register that could shift either left or right and what control signals would you need? 23 Example: 74LS94 S S LIN D B C A RIN D C B A S S Action hold shift right shift left load A* B* C* D* A B C D RIN A B C B C D LIN A B C D Shift left is from A to D Shift right is from D to A is asynchronous 24 2
13 Verilog Description Of A Shift Register module shift4 (D, LD, LI, Ck, ); input [3:] D; input LD, LI, Ck; output [3:] ; reg [3:] ; Ck) if (LD) <= D; else begin [] <= []; [] <= [2]; [2] <= [3]; [3] <= LI; end endmodule 25 Ring Counters 26 3
14 SelfCorrecting Ring Counter 27 ohnson counter, switchtail counter, moebius counter 28 4
15 SelfCorrecting ohnson Counter Odd Length ohnson Counter This counter is also selfcorrecting Review Register control signals and assertions. Binary counters and their operations. Reset, Load, Output Enable. Counter timing; maximum clock frequency. Modn counters Synchronous vs. asynchronous load and reset signals. Shift registers and shift register counters. Ring counters, ohnson counters, etc Selfcorrecting counters Counter realization of sequential circuits 3 5
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