# Finite State Machine. RTL Hardware Design by P. Chu. Chapter 10 1

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1 Finite State Machine Chapter 10 1

2 Outline 1. Overview 2. FSM representation 3. Timing and performance of an FSM 4. Moore machine versus Mealy machine 5. VHDL description of FSMs 6. State assignment 7. Moore output buffering 8. FSM design examples Chapter 10 2

3 1. Overview on FSM Contain random logic in next-state logic Used mainly used as a controller in a large system Mealy vs Moore output Chapter 10 3

4 2. Representation of FSM State diagram Chapter 10 4

5 E.g. a memory controller Chapter 10 5

6 ASM (algorithmic state machine) chart Flowchart-like diagram Provide the same info as an FSM More descriptive, better for complex description ASM block One state box One ore more optional decision boxes: with T or F exit path One or more conditional output boxes: for Mealy output Chapter 10 6

7 Chapter 10 7

8 State diagram and ASM chart conversion E.g. 1. Chapter 10 8

9 E.g. 2. Chapter 10 9

10 E.g. 3. Chapter 10 10

11 E.g. 4. Chapter 10 11

12 E.g. 6. Chapter 10 12

13 Difference between a regular flowchart and ASM chart: Transition governed by clock Transition done between ASM blocks Basic rules: For a given input combination, there is one unique exit path from the current ASM block The exit path of an ASM block must always lead to a state box. The state box can be the state box of the current ASM block or a state box of another ASM block. Chapter 10 13

14 Incorrect ASM charts: Chapter 10 14

15 Chapter 10 15

16 3. Performance of FSM Similar to regular sequential circuit Chapter 10 16

17 Sample timing diagram Chapter 10 17

18 Chapter 10 18

19 4. Moore vs Mealy output Moore machine: output is a function of state Mealy machine: output function of state and output From theoretical point of view Both machines have similar computation capability Implication of FSM as a controller? Chapter 10 19

20 E.g., edge detection circuit A circuit to detect the rising edge of a slow strobe input and generate a short (about 1-clock period) output pulse. Chapter 10 20

21 Three designs: Chapter 10 21

22 Chapter 10 22

23 Comparison Mealy machine uses fewer states Mealy machine responds faster Mealy machine may be transparent to glitches Which one is better? Types of control signal Edge sensitive E.g., enable signal of counter Both can be used but Mealy is faster Level sensitive E.g., write enable signal of SRAM Moore is preferred Chapter 10 23

24 VHDL Description of FSM Follow the basic block diagram Code the next-state/output logic according to the state diagram/asm chart Use enumerate data type for states Chapter 10 24

25 E.g. 6. Chapter 10 25

26 Chapter 10 26

27 Chapter 10 27

28 Chapter 10 28

29 Chapter 10 29

30 Chapter 10 30

31 Chapter 10 31

32 Combine next-state/output logic together Chapter 10 32

33 Chapter 10 33

34 Chapter 10 34

35 6. State assignment State assignment: assign binary representations to symbolic states In a synchronous FSM All assignments work Good assignment reduce the complexity of next-state/output logic Typical assignment Binary, Gray, one-hot, almost one-hot Chapter 10 35

36 Chapter 10 36

37 State assignment in VHDL Implicit: use user attributes enum_encoding Explicit: use std_logic_vector for the register Chapter 10 37

38 Chapter 10 38

39 Chapter 10 39

40 Handling the unused state Many binary representations are not used What happens if the FSM enters an unused state? Ignore the condition Safe (Fault-tolerant) FSM: got to an error state or return to the initial state. Easy for the explicit state assignment No portable code for the enumerated data type Chapter 10 40

41 6. Moore output buffering FSM as control circuit Sometimes fast, glitch-free signal is needed An extra output buffer can be added, but introduce one-clock delay Special schemes can be used for Moore output Clever state assignment Look-ahead output circuit Chapter 10 41

42 Potential problems of the Moore output logic: Potential hazards introduce glitches Increase the Tco delay (Tco = Tcq + Toutput) Can we get control signals directly from the register? Chapter 10 42

43 Clever state assignment Assigning state according to output signal patterns Output can be obtained from register directly Extra register bits may be needed Must use explicit state assignment in VHDL code to access individual register bit Difficult to revise and maintain Chapter 10 43

44 Chapter 10 44

45 VHDL code Chapter 10 45

46 Look-ahead output circuit Output buffer introduces one-clock delay The next value of Moore output can be obtained by using state_next signal Buffer the next value cancel out the one-clock delay More systematic and easier to revise and maintain Chapter 10 46

47 Chapter 10 47

48 Modification over original VHDL code: Add output buffer Use state_next to replace state_reg in Moore output logic Chapter 10 48

49 Chapter 10 49

50 7. FSM design examples Edge detector circuit Arbitrator (read) DRAM strobe signal generation Manchester encoding/decoding (read) FSM base binary counter Chapter 10 50

51 Edge detecting circuit (Moore) Chapter 10 51

52 Chapter 10 52

53 Use clever state assignment Chapter 10 53

54 Use look-ahead output Chapter 10 54

55 Edge detecting circuit (Mealy) Chapter 10 55

56 Chapter 10 56

57 Edge detecting circuit (direct implementation): edge occurs when previous value is 0 and new value is 1 Same as Mealy design with state assignment: zero => 0, one => 1 Chapter 10 57

58 Chapter 10 58

59 DRAM strobe signal generation E.g.,120ns DRAM (Trc=120ns): Tras=85ns, Tcas=20ns, Tpr=35ns Chapter 10 59

60 3 intervals has to be at least 65ns, 20 ns, and 35 ns A slow design: use a 65ns clock period 195 ns (3*65ns) read cycle The control signal is level-sensitive Chapter 10 60

61 Chapter 10 61

62 Should revise the code to obtain glitch-free output Chapter 10 62

63 A faster design: use a 20ns clock period 140 ns (7*20ns) read cycle mem' idle mem r1 ras_n<=0 c ras_n<=0 cas_n<=0 p1 r2 ras_n<=0 p2 r3 ras_n<=0 r4 ras_n<=0 Chapter 10 63

64 FSM-based binary counter: Free-running mod-16 counter Chapter 10 64

65 4-bit binary counter with features: Synchronous clear, load, enable Chapter 10 65

66 Chapter 10 66

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