Asynchronous Counters. Asynchronous Counters
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1 Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter operation, asynchronous means that the Flip-Flops within the counter are not connected in a way to cause all Flip-Flops states at exactly the same time they are wired in a way that links the clock of the next flipflop to the Q of the current device this causes the output count states to ripple through the counter November 25 ENGI 25/ELEC 24 Counter Design 2 ENGI 25/ELEC 24
2 Counters and State Machine Design November 25 2-Bit (MOD 4) Asynchronous Counter November 25 ENGI 25/ELEC 24 Counter Design 3 November 25 ENGI 25/ELEC 24 Counter Design 4 ENGI 25/ELEC 24 2
3 Counters and State Machine Design November 25 3-Bit (MOD 8) Asynchronous Counter November 25 ENGI 25/ELEC 24 Counter Design 5 November 25 ENGI 25/ELEC 24 Counter Design 6 ENGI 25/ELEC 24 3
4 Counters and State Machine Design November 25 ENGI 25/ELEC 24 4 November 25 ENGI 25/ELEC 24 Counter Design 7 Propagation Delay in Ripple Clocked Binary Counters November 25 ENGI 25/ELEC 24 Counter Design 8 4-Bit Counter State Table CLK QD QC QB QA
5 Counters and State Machine Design November 25 ENGI 25/ELEC 24 5 November 25 ENGI 25/ELEC 24 Counter Design 9 4-Bit Asynchronous Counter November 25 ENGI 25/ELEC 24 Counter Design MOD Counter State Table CLK QD QC QB QA
6 Counters and State Machine Design November 25 Asynchronous Decade (MOD ) Counter November 25 ENGI 25/ELEC 24 Counter Design MOD 2 Asynchronous Counter November 25 ENGI 25/ELEC 24 Counter Design 2 ENGI 25/ELEC 24 6
7 Counters and State Machine Design November 25 November 25 ENGI 25/ELEC 24 Counter Design A MOD 6 Counter November 25 ENGI 25/ELEC 24 Counter Design 4 ENGI 25/ELEC 24 7
8 Counters and State Machine Design November 25 Synchronous Counters ENGI 25 ELEC 24 Synchronous Counters The term synchronous refers to events that do occur simultaneously In communications, both ends must be connected telephone call with respect to counter operation, synchronous means that the counter is connected such that all the Flip- Flops change at the same time they are wired in a way that links all the flip-flop clock inputs together this causes the output count states to change at the same time There is a propagation delay, but they are typically very close in similar devices November 25 ENGI 25/ELEC 24 Counter Design 6 ENGI 25/ELEC 24 8
9 Counters and State Machine Design November 25 MOD 4 Synchronous Counter November 25 ENGI 25/ELEC 24 Counter Design 7 MOD 4 Counter Timing Diagram November 25 ENGI 25/ELEC 24 Counter Design 8 ENGI 25/ELEC 24 9
10 Counters and State Machine Design November 25 MOD 8 Synchronous Counter November 25 ENGI 25/ELEC 24 Counter Design 9 MOD Synchronous Counter November 25 ENGI 25/ELEC 24 Counter Design 2 ENGI 25/ELEC 24
11 Counters and State Machine Design November 25 MOD Timing Diagram November 25 ENGI 25/ELEC 24 Counter Design 2 Johnson Counter State Diagram November 25 ENGI 25/ELEC 24 Counter Design 22 ENGI 25/ELEC 24
12 Counters and State Machine Design November 25 Johnson Counter A Johnson counter is a special counter where the output of the last stage is inverted and fed back as input to the first stage. A pattern of bits equal in length circulates indefinitely. These counters are sometimes called "walking ring" counters, and find special applications. November 25 ENGI 25/ELEC 24 Counter Design 23 74LS63A 4-bit Binary Counter The counter can be synchronously preset to any four-bit binary number by When a LOW is applied to the LOAD input, the counter will assume the state of the data inputs on the next clock pulse The active-low CLR input synchronously RESETS all four flip- flops in the counter November 25 ENGI 25/ELEC 24 Counter Design 24 ENGI 25/ELEC 24 2
13 Counters and State Machine Design November 25 74LS63A Timing Diagram November 25 ENGI 25/ELEC 24 Counter Design 25 74LS6A November 25 ENGI 25/ELEC 24 Counter Design 26 ENGI 25/ELEC 24 3
14 Counters and State Machine Design November 25 November 25 ENGI 25/ELEC 24 Counter Design 27 November 25 ENGI 25/ELEC 24 Counter Design 28 ENGI 25/ELEC 24 4
15 Counters and State Machine Design November 25 November 25 ENGI 25/ELEC 24 Counter Design 29 State Machine Design ENGI 25/ELEC 24 5
16 Counters and State Machine Design November 25 State Machine Design The Figure above is the general diagram of a State Machine There are two basic components in a state machine, Memory which are usually JK Flip-Flops, and Combinational Logic To design a state machine, JK flip-flops are usually connected as a counter The following will demonstrate the design the logic necessary to allow the counter to sequence any desired binary pattern November 25 ENGI 25/ELEC 24 Counter Design 3 Gray Code State Diagram The figure on the left shows the progression of states and the input and outputs for a Gray Code Counter The arrow in the center shows the direction of the counter If we start at, the next state is From the next state is We progress through all possible states until the sequence repeats We use the State Diagram to create the Next State Table November 25 ENGI 25/ELEC 24 Counter Design 32 ENGI 25/ELEC 24 6
17 Counters and State Machine Design November 25 Gray Code Next State Table November 25 ENGI 25/ELEC 24 Counter Design 33 Gray Code Transition Table X = Don t Care (may be or ) November 25 ENGI 25/ELEC 24 Counter Design 34 ENGI 25/ELEC 24 7
18 Counters and State Machine Design November 25 K-MAP for Gray Code Transistion November 25 ENGI 25/ELEC 24 Counter Design 35 BCD Counter Design November 25 ENGI 25/ELEC 24 Counter Design 36 ENGI 25/ELEC 24 8
19 Counters and State Machine Design November 25 BCD Counter Design November 25 ENGI 25/ELEC 24 Counter Design 37 ENGI 25/ELEC 24 9
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