W/ C V GS Gate-to-Source Voltage ± 20 dv/dt Peak Diode Recovery f 10. V/ns T J. mj I AR. Thermal Resistance Symbol Parameter Typ. Max.
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1 PD 9734 HEXFET Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits G D V DSS R DS(on) typ. max. I D (Silicon Limited) V 2.m: 2.6m: 29A c Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l LeadFree S I D (Package Limited) D S D G 95A TO247AC G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V V (Silicon Limited) 29c I T C = C Continuous Drain Current, V V (Silicon Limited) 2 I T C = 25 C Continuous Drain Current, V V (Wire Bond Limited) 95 A I DM Pulsed Drain Current d 2 P C = 25 C Maximum Power Dissipation 52 W Linear Derating Factor 3.4 W/ C V GS GatetoSource Voltage ± 2 V dv/dt Peak Diode Recovery f V/ns Operating Junction and 55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 3 C (.6mm from case) Mounting torque, 632 or M3 screw lbxin (.Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 74 mj I AR Avalanche Currentd See Fig. 4, 5, 22a, 22b, A E AR Repetitive Avalanche Energy g mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc JunctiontoCase k.29 R θcs CasetoSink, Flat Greased Surface.24 C/W R θja JunctiontoAmbient jk 4 5/2/8
2 = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage V V GS = V, I D = 25μA ΔV (BR)DSS /Δ Breakdown Voltage Temp. Coefficient.9 V/ C Reference to 25 C, I D = 5mAd R DS(on) Static DraintoSource OnResistance mω V GS = V, I D = 8A g V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 25μA I DSS DraintoSource Leakage Current 2 μa V DS = V, V GS = V 25 V DS = 8V, V GS = V, = 25 C I GSS GatetoSource Forward Leakage na V GS = 2V GatetoSource Reverse Leakage V GS = 2V R G Internal Gate Resistance.8 Ω = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 3 S Q g Total Gate Charge nc Q gs GatetoSource Charge 8 Q gd GatetoDrain ("Miller") Charge 89 Q sync Total Gate Charge Sync. (Q g Q gd ) 27 t d(on) TurnOn Delay Time 52 ns t r Rise Time 23 t d(off) TurnOff Delay Time 6 t f Fall Time 26 C iss Input Capacitance 986 pf C oss Output Capacitance 36 C rss Reverse Transfer Capacitance 54 C oss eff. (ER) Effective Output Capacitance (Energy Related) 55 C oss eff. (TR) Effective Output Capacitance (Time Related)h 9 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 29c A Conditions V DS = 5V, I D = 8A I D = 8A V DS =5V V GS = V g I D = 8A, V DS =V, V GS = V V DD = 65V I D = 8A R G = 2.7Ω V GS = V g V GS = V V DS = 5V ƒ = khz, See Fig. 5 V GS = V, V DS = V to 8V i, See Fig. V GS = V, V DS = V to 8V h Conditions MOSFET symbol (Body Diode) showing the I SM Pulsed Source Current 2 A integral reverse G (Body Diode)d pn junction diode. V SD Diode Forward Voltage.3 V = 25 C, I S = 8A, V GS = V g t rr Reverse Recovery Time ns = 25 C V R = 85V, = 25 C I F = 8A Q rr Reverse Recovery Charge 37 nc = 25 C di/dt = A/μs g 42 = 25 C I RRM Reverse Recovery Current 6.9 A = 25 C t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) D S Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 95A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN4) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by max, starting = 25 C, L =.45mH R G = 25Ω, I AS = 8A, V GS =V. Part not recommended for use above this value. I SD 8A, di/dt 6A/μs, V DD V (BR)DSS, 75 C. Pulse width 4μs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. ˆ When mounted on " square PCB (FR4 or G Material). For recom mended footprint and soldering techniques refer to application note #AN994. R θ is measured at approximately 9 C 2
3 C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (Α) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.5V BOTTOM 4.V VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.5V BOTTOM 4.V 4.V 4.V 6μs PULSE WIDTH Tj = 25 C.. V DS, DraintoSource Voltage (V) 6μs PULSE WIDTH Tj = 75 C. V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.5 I D = 8A V GS = V = 75 C 2. = 25 C.5 V DS = 25V 6μs PULSE WIDTH V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics , Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature V GS = V, f = khz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 6 2 I D = 8A V DS = 8V V DS = 5V V DS = 2V 2 Ciss Coss 4 Crss V DS, DraintoSource Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. DraintoSource Voltage Fig 6. Typical Gate Charge vs. GatetoSource Voltage 3
4 Energy (μj) E AS, Single Pulse Avalanche Energy (mj) I D, Drain Current (A) V (BR)DSS, DraintoSource Breakdown Voltage I D, DraintoSource Current (A) I SD, Reverse Drain Current (A) = 75 C = 25 C V GS = V V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage LIMITED BY PACKAGE 2 LIMITED BY PACKAGE Fig 8. Maximum Safe Operating Area I D = 5mA OPERATION IN THIS AREA LIMITED BY R DS (on) μsec msec msec Tc = 25 C Tj = 75 C DC Single Pulse.. V DS, DraintoSource Voltage (V) T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature , Junction Temperature ( C) Fig. DraintoSource Breakdown Voltage I D TOP 3A 4A BOTTOM 8A V DS, DraintoSource Voltage (V) Starting, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy Vs. DrainCurrent 4
5 E AR, Avalanche Energy (mj) Avalanche Current (A) Thermal Response ( Z thjc )... D = SINGLE PULSE ( THERMAL RESPONSE ) R R 2 R 3 R R 2 R 3 τ J τ J τ τ τ 2 τ 3 τ 2 τ 3 Ci= τi/ri Ci= τi/ri. E6 E5.... t, Rectangular Pulse Duration (sec) Ri ( C/W) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig 3. Maximum Effective Transient Thermal Impedance, JunctiontoCase τ C τ τι (sec) Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 5 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤ j = 25 C and Tstart = 5 C..E6.E5.E4.E3.E2.E TOP Single Pulse BOTTOM % Duty Cycle I D = 8A Starting, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature tav (sec) Fig 4. Typical Avalanche Current vs.pulsewidth Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. ΔT = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av 5
6 Q RR (nc) I RRM (A) Q RR (nc) V GS (th) Gate threshold Voltage (V) I RRM (A) I D =.A I D =.ma I D = 25μA , Temperature ( C ) Fig 6. Threshold Voltage Vs. Temperature I F = 72A 8 V R = 85V = 25 C = 25 C di f / dt (A / μs) Fig. 7 Typical Recovery Current vs. di f /dt I F = 8A 8 V R = 85V = 25 C = 25 C di f / dt (A / μs) Fig. 8 Typical Recovery Current vs. di f /dt 5 I F = 72A V R = 85V = 25 C = 25 C di f / dt (A / μs) Fig. 9 Typical Stored Charge vs. di f /dt 2 5 I F = 8A V R = 85V = 25 C = 25 C di f / dt (A / μs) Fig. 2 Typical Stored Charge vs. di f /dt 6
7 D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD ReApplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T I AS.Ω V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G V DD VV GS Pulse Width µs Duty Factor. % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5KΩ Vgs 2V.2μF.3μF V GS D.U.T. V DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 7
8 TO247AC Package Outline Dimensions are shown in millimeters (inches) TO247AC Part Marking Information EXAMPLE: THIS IS AN IRFPE3 WIT H AS S E MB L Y LOT CODE 5657 ASSEMBLED ON WW 35, 2 IN THE ASSEMBLY LINE "H" Note: "P" in assembly line position indicates "LeadFree" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFPE3 35H PART NUMBER DATE CODE YEAR = 2 WEEK 35 LINE H TO247AC packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. 5/8 8
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