AOD472 N-Channel Enhancement Mode Field Effect Transistor
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- Homer Thomas
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1 NChannel Enhancement Mode Field Effect Transistor General Description Features.4 The AOD472 uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. This device is suitable for use in PWM, load switching and general purpose applications. V DS (V) = 25V I D = 55A (VGS = V) R DS(ON) <6 mω (V GS = V) R DS(ON) <9.5 mω (VGS = 4.5V) % UIS Tested % R g Tested 93 8 Top View D TO252 DPAK Bottom View D G S S G G S Absolute Maximum Ratings T A =25 C unless otherwise noted Parameter Symbol Maximum DrainSource Voltage 25 GateSource Voltage Continuous Drain T C =25 C Current G T C = C Pulsed Drain Current C V DS V GS I DM I SM I AR E AR 55 I D 43 2 Pulsed Forward Diode Current C 2 Avalanche Current C 5 Repetitive avalanche energy L=.mH C 25 T C =25 C 6 Power Dissipation B P D T C = C 3 T A =25 C 2.5 Power Dissipation A P DSM T A =7 C.6 Junction and Storage Temperature Range T J, T STG 55 to 75 ±2 Units V V A mj W W C Thermal Characteristics Parameter Symbol Typ Max Units Maximum JunctiontoAmbient A t s 5 2 C/W Maximum JunctiontoAmbient A R θja SteadyState 4 5 C/W Maximum JunctiontoCase B SteadyState R θjc C/W
2 Electrical Characteristics (T J =25 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage I D =25uA, V GS =V 25 V I DSS Zero Gate Voltage Drain Current V DS =2V, V GS =V T J =55 C 5 µa I GSS GateBody leakage current V DS =V, V GS =±2V na V GS(th) Gate Threshold Voltage V DS =V GS, I D =25µA V I D(ON) On state drain current V GS =V, V DS =5V 5 A V GS =V, I D =3A 5 6 R DS(ON) Static DrainSource OnResistance T J =25 C 7.5 mω V GS =4.5V, I D =2A g FS Forward Transconductance V DS =5V, I D =2A 49 S V SD Diode Forward Voltage I S =A, V GS =V.74 V I S Maximum BodyDiode Continuous Current 5 A DYNAMIC PARAMETERS C iss Input Capacitance pf C oss Output Capacitance V GS =V, V DS =2.5V, f=mhz pf C rss Reverse Transfer Capacitance 28 4 pf R g Gate resistance V GS =V, V DS =V, f=mhz.86.5 Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge 4 5 nc Q g (4.5V) Total Gate Charge 2 25 nc Q gs Gate Source Charge V GS =V, V DS =2.5V, I D =2A nc Q gsvth Gate Source Charge at Vth nc Q gd Gate Drain Charge nc t D(on) TurnOn DelayTime 7.5 ns t r TurnOn Rise Time V GS =V, V DS =2.5V, 22 ns t D(off) TurnOff DelayTime R L =.68Ω, R GEN =3Ω ns t f TurnOff Fall Time 8 6 ns t rr Body Diode Reverse Recovery Time I F =2A, di/dt=a/µs 3 36 ns Q rr Body Diode Reverse Recovery Charge I F =2A, di/dt=a/µs 9 23 nc A: The value of R θja is measured with the device mounted on in 2 FR4 board with 2oz. Copper, in a still air environment with T A =25 C. The Power dissipation P DSM is based on R θja and the maximum allowed junction temperature of 5 C. The value in any given application depends on the user's specific board design, and the maximum temperature of 75 C may be used if the PCB allows it. B. The power dissipation P D is based on T J(MAX) =75 C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C: Repetitive rating, pulse width limited by junction temperature T J(MAX) =75 C. D. The R θja is the sum of the thermal impedence from junction to case R θjc and case to ambient. E. The static characteristics in Figures to 6 are obtained using <3 µs pulses, duty cycle.5% max. F. These curves are based on the junctiontocase thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) =75 C. G. The maximum current rating is limited by bondwires. H. These tests are performed with the device mounted on in 2 FR4 board with 2oz. Copper, in a still air environment with T A =25 C. The SOA curve provides a single pulse rating. *This device is guaranteed green after data code 8X (Sep ST 28). Rev9: Feb 2 THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
3 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 2 6 V 6V 6 5 V DS =5V I D (A) V 4.5V 3.5V V GS =2.5 I D (A) C.4 25 C V DS (Volts) Fig : OnRegion Characteristics V GS (Volts) Figure 2: Transfer Characteristics 93 8 R DS(ON) (mω) V GS =4.5V V GS =V I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage Normalized OnResistance V GS =V, 3A V GS =4.5V, 2A Temperature ( C) Figure 4: OnResistance vs. Junction Temperature 2.E2 I D =2A.E.E 25 C R DS(ON) (mω) C 25 C I S (A).E.E2.E3.E4 25 C V GS (Volts) Figure 5: OnResistance vs. GateSource Voltage.E V SD (Volts) Figure 6: BodyDiode Characteristics
4 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 3 V GS (Volts) V DS =2.5V I D =2A Capacitance (pf) C oss C iss Q g (nc) Figure 7: GateCharge Characteristics T J(Max) =75 C, T C =25 C C rss V DS (Volts) Figure 8: Capacitance Characteristics 93 8 I D (Amps) R DS(ON) limited DC µs µs ms Power (W) T J(Max) =75 C T C =25 C 2.. V DS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note F) Figure : Single Pulse Power Rating JunctiontoCase (Note F) Z θjc Normalized Transient Thermal Resistance. D=T on /T T J,PK =T C P DM.Z θjc.r θjc R θjc =2.5 C/W In descending order D=.5,.3,.,.5,.2,., single pulse T Single Pulse Figure : Normalized Maximum Transient Thermal Impedance (Note F) P D T on
5 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS I D (A), Peak Avalanche Current Time in avalanche, t A (s) Figure 2: Single Pulse Avalanche capability 6 T A =5 C t A L I D = BV V T A =25 C DD Power Dissipation (W) T CASE ( C) Figure 3: Power Derating (Note B) T A =25 C Current rating I D (A) Power (W) T CASE ( C) Figure 4: Current Derating (Note B) Figure 5: Single Pulse Power Rating JunctiontoAmbient (Note H) Z θja Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T A P DM.Z θja.r θja R θja =5 C/W In descending order D=.5,.3,.,.5,.2,., single pulse Single Pulse T on T P D Figure 6: Normalized Maximum Transient Thermal Impedance (Note H)
6 Gate Charge Test Circuit & W aveform Qg V Qgs Qgd Ig Charge Resistive Switching Test Circuit & Waveforms RL Rg 9% % td(on) t r t d(off) t f t on t off Unclamped Inductive Switching (UIS) Test Circuit & Waveforms L 2 E = /2 LI AR AR BV DSS Id Rg Id I AR Diode Recovery Test Circuit & Waveforms Q = Idt rr Ig Isd L Isd I F di/dt I RM t rr
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