AUTOMOTIVE MOSFET TO-220AB IRF540Z A I DM. 140 P C = 25 C Power Dissipation 92 Linear Derating Factor V GS Gate-to-Source Voltage ± 20
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1 Features Advanced Process Technology Ultra Low On-Resistance 175 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax AUTOMOTIVE MOSFET Description Specifically designed for Automotive applications, this HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low onresistance per silicon area. Additional features of this design are a 175 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. G TO-22AB IRF54Z PD HEXFET Power MOSFET D S D 2 Pak IRF54ZS IRF54Z IRF54ZS IRF54ZL V DSS = V R DS(on) = 26.5mΩ I D = 36A TO-262 IRF54ZL Absolute Maximum Ratings I T C = 25 C Parameter Continuous Drain Current, V V (Silicon Limited) Units I T C = C Continuous Drain Current, V V 25 A I DM Pulsed Drain Current c 14 P C = 25 C Power Dissipation 92 W Linear Derating Factor.61 W/ C V GS Gate-to-Source Voltage ± 2 V E AS (Thermally limited) Single Pulse Avalanche Energyd 83 mj E AS (Tested ) Single Pulse Avalanche Energy Tested Value h 12 I AR Avalanche Currentc See Fig.12a, 12b, 15, 16 A E AR Repetitive Avalanche Energy g mj T J Operating Junction and -55 to T STG Storage Temperature Range C Soldering Temperature, for seconds 3 (1.6mm from case ) lbfyin (1.1Nym) Mounting Torque, 6-32 or M3 screw i Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.64 C/W R θcs Case-to-Sink, Flat Greased Surface i.5 R θja Junction-to-Ambient i 62 R θja Junction-to-Ambient (PCB Mount) j Max. 36 /31/3
2 IRF54Z/S/L Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage V Conditions V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.93 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance mω V GS = V, I D = 22A e V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 25µA gfs Forward Transconductance 36 V V DS = 25V, I D = 22A I DSS Drain-to-Source Leakage Current 2 µa V DS = V, V GS = V 25 V DS = V, V GS = V, T J = 125 C I GSS Gate-to-Source Forward Leakage 2 na V GS = 2V Gate-to-Source Reverse Leakage -2 V GS = -2V Q g Total Gate Charge I D = 22A Q gs Gate-to-Source Charge 9.7 nc V DS = 8V Q gd Gate-to-Drain ("Miller") Charge 15 V GS = V e t d(on) Turn-On Delay Time 15 V DD = 5V t r Rise Time 51 I D = 22A t d(off) Turn-Off Delay Time 43 ns R G = 12 Ω t f Fall Time 39 V GS = V e L D Internal Drain Inductance 4.5 Between lead, D nh 6mm (.25in.) L S Internal Source Inductance 7.5 from package G and center of die contact S C iss Input Capacitance 177 V GS = V C oss Output Capacitance 18 V DS = 25V C rss Reverse Transfer Capacitance pf ƒ = 1.MHz C oss Output Capacitance 73 V GS = V, V DS = 1.V, ƒ = 1.MHz C oss Output Capacitance 1 V GS = V, V DS = 8V, ƒ = 1.MHz C oss eff. Effective Output Capacitance 17 V GS = V, V DS = V to 8V f Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 36 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 14 integral reverse (Body Diode)Ãc p-n junction diode. V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 22A, V GS = V e t rr Reverse Recovery Time 33 5 ns T J = 25 C, I F = 22A, V DD = 5V Q rr Reverse Recovery Charge nc di/dt = A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2
3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRF54Z/S/L VGS TOP 15V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V VGS TOP 15V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 4.5V 4.5V 6µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 1 6µs PULSE WIDTH Tj = 175 C.1 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 8 T J = 175 C T J = 25 C V DS = 25V 6µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Gfs, Forward Transconductance (S) T J = 175 C T J = 25 C V DS = V 38µs PULSE WIDTH I D, Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance Vs. Drain Current 3
4 I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRF54Z/S/L V GS = V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd Ciss I D = 22A V DS = 8V VDS= 5V VDS= 2V Coss Crss 1 V DS, Drain-to-Source Voltage (V) 4 FOR TEST CIRCUIT SEE FIGURE Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage. OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A). T J = 175 C. 1. T J = 25 C V GS = V Tc = 25 C Tj = 175 C Single Pulse µsec 1msec msec 1 V SD, Source-toDrain Voltage (V) V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4
5 Thermal Response ( Z thjc ) I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) IRF54Z/S/L I D = 22A V GS = V T J, Junction Temperature ( C) T J, Junction Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig. Normalized On-Resistance Vs. Temperature 1.1 D = SINGLE PULSE ( THERMAL RESPONSE ).1 1E-6 1E t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5
6 V GS(th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) IRF54Z/S/L R G V DS 2V V GS tp L D.U.T I AS.1Ω 15V DRIVER + - V DD A I D TOP 8.3A 14A BOTTOM 2A Fig 12a. Unclamped Inductive Test Circuit tp V (BR)DSS Starting T J, Junction Temperature ( C) I AS Fig 12b. Unclamped Inductive Waveforms Q G Fig 12c. Maximum Avalanche Energy Vs. Drain Current V Q GS Q GD 4. V G 3.5 Charge Fig 13a. Basic Gate Charge Waveform I D = 25µA 1K DUT L VCC T J, Temperature ( C ) Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature 6
7 E AR, Avalanche Energy (mj) Avalanche Current (A) IRF54Z/S/L Duty Cycle = Single Pulse.1 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses E-8 1.E-7 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth TOP Single Pulse BOTTOM % Duty Cycle I D = 2A Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-5 at 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure 11) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc Fig 16. Maximum Avalanche Energy I av = 2DT/ [1.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av 7
8 IRF54Z/S/L + - D.U.T + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - + Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. + - V DD V Pulse Width 1 µs Duty Factor.1 % Fig 18a. Switching Time Test Circuit V DS 9% % V GS t d(on) t r t d(off) t f Fig 18b. Switching Time Waveforms 8
9 IRF54Z/S/L TO-22AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.3).54 (.415).29 (.45) 3.78 (.149) 3.54 (.139) - A (.185) 4.2 (.165) - B (.52) 1.22 (.48) (.6) (.584) (.255) 6. (.24) (.45) MIN LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 14.9 (.555) (.53) 4.6 (.16) 3.55 (.14) 3X 1.4 (.55) 1.15 (.45) 3X.93 (.37).69 (.27).36 (.14) M B A M 3X 2.92 (.115) 2.64 (.4).55 (.22).46 (.18) 2.54 (.) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO-22AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-22AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C For GB Production EXAMPLE: THIS IS AN IRF LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO PART NUMBER LOT CODE DATE CODE 9
10 IRF54Z/S/L D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information THIS IS AN IRF53S WITH LOT CODE 824 ASSEMBLED ON WW 2, 2 IN THE ASSEMBLY LINE "L" For GB Production THIS IS AN IRF53S WITH LOT CODE 824 ASSEMBLED ON WW 2, 2 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE INTERNATIONAL RECTIFIER LOGO F53S F53S PART NUMBER DATE CODE YEAR = 2 WEEK 2 LINE L PART NUMBER LOT CODE DATE CODE
11 IRF54Z/S/L TO-262 Package Outline Dimensions are shown in millimeters (inches) IGBT 1- GATE 2- COLLEC- TOR TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 1789 INTERNATIONAL ASSEMBLED ON WW 19, 1997 RECTIFIER IN THE ASSEMBLY LINE "C" LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C 11
12 IRF54Z/S/L D 2 Pak Tape & Reel Information TRR 1.6 (.63) 1.5 (.59) 4. (.161) 3.9 (.153) 1.6 (.63) 1.5 (.59).368 (.145).342 (.135) FEED DIRECTION TRL 1.85 (.73) 1.65 (.65).9 (.429).7 (.421) 11.6 (.457) 11.4 (.449) 16. (.634) 15.9 (.626) 1.75 (.69) 1.25 (.49) (.69) (.61) 24.3 (.957) 23.9 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.5 (.532) 12.8 (.54) 27.4 (1.79) 23.9 (.941) (14.173) MAX. 6. (2.362) MIN. NOTES : 1. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (1.39) 24.4 (.961) (1.197) MAX. 4 Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by T Jmax, starting T J = 25 C, L =.46mH R G = 25Ω, I AS = 2A, V GS =V. Part not recommended for use above this value. ƒ Pulse width 1.ms; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. TO-22AB package is not recommended for Surface Mount Application. Limited by T Jmax, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. % tested to this value in production. This is only applied to TO-22AB pakcage. ˆ This is applied to D 2 Pak, when mounted on 1" square PCB (FR- 4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q1]market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. /3 12
13 Note: For the most current drawings please refer to the IR website at:
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