Basic bistable element. Chapter 6. Latches vs. flip-flops. Flip-flops
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1 Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. Flip-Flops and Simple Flip-Flop Applications.. Huang, 24 igital Logic esign Flip-flops A flip-flop is a bistable device, with inputs, that remains in a given state as long as power is applied and until input signals are applied to cause its output to change. Latches vs. flip-flops Latches are flip-flops for which the timing of the output changes are not controlled. For a latch, the output essentially responds immediately to changes on the input lines (and possibly the presence of a clock pulse). A flip-flop is designed to change its output at the edge of a controlling clock signal... Huang, 24 igital Logic esign 2.. Huang, 24 igital Logic esign 3 SR (Set-Reset) latch Next state If denotes the present state of a memory device, i.e., the state at the time the input signals are applied, we shall use + or (t+) to denote the next state, i.e., the new state assumed by the device in response to the input signals... Huang, 24 igital Logic esign 4.. Huang, 24 igital Logic esign 5
2 R S latch Gated SR latch.. Huang, 24 igital Logic esign 6.. Huang, 24 igital Logic esign 7 Gated latch iming considerations Propagation delays Minimum pulse width Setup and hold time.. Huang, 24 igital Logic esign 8.. Huang, 24 igital Logic esign 9 Propagation delay he time it takes a change in the input signal to produce a change in the output signal. Minimum pulse width he minimum amount of time a signal must be applied in order to produce a desired result... Huang, 24 igital Logic esign.. Huang, 24 igital Logic esign
3 Setup and hold times o achieve a satisfactory operation of a gated latch, constraints are normally placed on the time intervals between input changes. he minimum time the input signal must be held fixed before and after the latching action is called the setup time and hold time, respectively. - and -type flip-flops In addition to the SR-type and -type flipflops discussed above, there are two other types, viz., - and -type flip-flops... Huang, 24 igital Logic esign 2.. Huang, 24 igital Logic esign 3 flip-flops flip-flop ( t+ ) () t (a) ircuit A flip-flop works just like an SR flipflop if we consider input as S(et) input and input as R(eset) input, except when both S and R inputs are set to, the output simply flips over. () t (b) ruth table (c) Graphical symbol.. Huang, 24 igital Logic esign 4.. Huang, 24 igital Logic esign 5 -type flip-flops A flip-flop is obtained from a flip-flop by tying the and inputs together to form the input. ' ' Flip-flops here are four different types of flip-flops: SR,,, and types. he properties of these flip-flops are summarized in the following 4 slides. he function and application tables are also known as characteristic and excitation tables, respectively... Huang, 24 igital Logic esign 6.. Huang, 24 igital Logic esign 7
4 SR-type flip-flop -type flip-flop S R ' (t+) = S + R' SR = ' (t+) = Graphic symbol haracteristic equation Graphic symbol haracteristic equation S R (t+)? Function table (t+) S Application table R X X (t+) (t+) Function table Application table.. Huang, 24 igital Logic esign 8.. Huang, 24 igital Logic esign 9 -type flip-flop -type flip-flop ' (t+) = ' + ' ' (t+) = ' + ' Graphic symbol haracteristic equation Graphic symbol haracteristic equation (t+) ' Function table (t+) Application table X X X X (t+) ' Function table (t+) Application table.. Huang, 24 igital Logic esign 2.. Huang, 24 igital Logic esign 2 Positive and negative edge Edge-triggered flip-flops he transition of a control signal (clock pulse) from its low to high value ( to ) in positive logic is called the positive edge of the control signal, while the transition from high to low ( to ) is called the negative edge... Huang, 24 igital Logic esign 22 Edge triggered flip-flops use just one of the edges of the clock pulse to affect the reading of the input lines. hese flip-flops are designed to be triggered by either the positive or negative edge. In analyzing the behavior of an asynchronous sequential circuit, one often needs to know which edge trigger the flip-flops used... Huang, 24 igital Logic esign 23
5 lk a a level sensitive latch Serial-in, serial-out unidirectional shift register (a) ircuit b b c c positive-edgetriggered negative-edgetriggered a b c (b) iming diagram.. Huang, 24 igital Logic esign 24.. Huang, 24 igital Logic esign 25 Serial-in, parallel-out unidirectional shift register Parallel-in unidirectional shift register.. Huang, 24 igital Logic esign 26.. Huang, 24 igital Logic esign 27 Universal shift register 4-bit binary ripple (asynchronous) counter with positive-edge triggered flip-flops... Huang, 24 igital Logic esign 28.. Huang, 24 igital Logic esign 29
6 A 3-bit up-counter 2 2 (a) ircuit Analysis method: onstruct a list of state changes as follows.. Assume that the counter starts with some values, say,. 2. Because = for, will change at the arrival of every clock pulse. omplete the listing for. 3. Because =, and because the flip-flop is triggered by a positive going clock input, for, changes its content whenever changes from to. 4. o the same for the listing for 2. 2 ount (b) iming diagram he flip-flops are triggered by positive going edge of the clock input... Huang, 24 igital Logic esign 3.. Huang, 24 igital Logic esign 3 Analysis method: 2 A 3-bit down-counter 2 (a) ircuit onstruct a list of state changes as follows.. Assume that the counter starts with some values, say,. 2. Because = for, will change at the arrival of every clock pulse. omplete the listing for. 3. Because =, and because the flip-flop is triggered by a positive going clock input, for, it changes its content whenever changes from to. 4. o the same for the listing for 2. 2 ount (b) iming diagram he flip-flops are triggered by positive going edge of the clock input.. Huang, 24 igital Logic esign 32.. Huang, 24 igital Logic esign 33 he following synchronous counter can be analyzed similarly Four-bit synchronous binary counter Huang, 24 igital Logic esign 34.. Huang, 24 igital Logic esign 35
7 Four-bit synchronous binary counter variation Four-bit synchronous binary counter with parallel load inputs.. Huang, 24 igital Logic esign 36.. Huang, 24 igital Logic esign 37 Synchronous mod- counter 8-bit synchronous binary counter constructed from two 4-bit synchronous binary counters.. Huang, 24 igital Logic esign 38.. Huang, 24 igital Logic esign 39 Mod-4 ring counter Mod-8 twisted-ring counter (or ohnson counter).. Huang, 24 igital Logic esign 4.. Huang, 24 igital Logic esign 4
8 Mod-7 twisted-ring counter ontrol signal generators A control signal generator is a sequential circuit that generate a sequence of bit patterns, each of which contains only one. It is used to activate various devices in turn. Shown in the next slide are the wave forms of 4-bit control signals... Huang, 24 igital Logic esign 42.. Huang, 24 igital Logic esign 43 4-bit control pulses ontrol-signal generator (continued) P 2 here are three ways to generate control signals (with n bits):. Use an n-bit ring counter (need n flip-flops) 2. Use a binary counter and a decoder ( need k flip-flops and n AN gates with k inputs, where n 2 k ) 3. Use a ohnson counter (need n/2 flip-flops) and n 2-input AN gates. 3.. Huang, 24 igital Logic esign 44.. Huang, 24 igital Logic esign n y y y 2 y 3 2-to-4 decoder w w En lear Up-counter Reset A part of the control circuit for the processor.. Huang, 24 igital Logic esign 46 Reset An n-bit ohnson counter, augmented with 2n AN-gates, will generate 2n-bit control signals. It uses n/2 flip-flops, 2n 2-input, AN gates. Figure 7.3 ohnson counter.. Huang, 24 igital Logic esign 47
9 A B ounting sequence of a 3-bit ohnson counter A B. A' ' A B' B ' 2 Reset A A' 3 4 Figure 7.3 A 3-bit ohnson counter A ohnson counter, augmented with a bank of AN gates, becomes a control-signal generator B' 5.. Huang, 24 igital Logic esign 48.. Huang, 24 igital Logic esign 49 Synchronous counters A synchronous counter is a special kind of synchronous sequential circuit, the analysis and design of such a circuit will be discussed in the next chapter... Huang, 24 igital Logic esign 5
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