Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann


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1 Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann
2 Chapter Overview 7 Registers and Load Enable 72 Register Transfers 73 Register Transfer Operations 74 A Note for VHDL and Verilog Users Only 75 Microoperations 76 Microoperatrions on a Single Register 77 Register Cell Design 78 Multiplexer and BusBased Transfer for Multiple Registers 79 Serial Transfer and Microoperations 7 HDL Representation for Shift Registes and Counters VHDL 7 HDL Representation for Shift Registes and Counters Verilog 72 Chapter Summary J.J. Shann 72
3 Part I: Registers and Counters 7 Registers and Load Enable 76 Microoperatrions on a Single Register (Shift registers, Ripple counter, Synchronous binary counters, other counters) Part II: Register Transfers 72 Register Transfers 73 Register Transfer Operations 75 Microoperations 77 Register Cell Design 76 Microoperatrions on a Single Register (MultiplexerBased Transfers) 78 Multiplexer and BusBased Transfer for Multiple Registers 79 Serial Transfer and Microoperations 72 Chapter Summary J.J. Shann 73
4 Part I Registers and Counters J.J. Shann
5 Clocked seq ckt: sync seq ckt consists of a group of flipflops and combinational gates connected to form a feedback path. Flipflops + Combinational gates (essential) (optional) Register: consists of a group of flipflops capable of storing binary information and gates that determine how the information is transferred into the register. Counter: is essentially a register that goes through a predetermined sequence of states. J.J. Shann 75
6 Lecture Contents A. Simplest register ( 7) B. Register with parallel load ( 7) C. Shift registers ( 76) D. Ripple counter ( 76) E. Synchronous binary counters ( 76) F. Other counters ( 76) J.J. Shann 76
7 A. Simplest Register ( 7) Simplest register: consists of only flipflops w/o any gates. E.g.: a 4bit register with asynchronous clear input J.J. Shann 77
8 B. Register w/ Parallel Load ( 7) Load Approach : Load control input through the C inputs of the ffs clock gating Approach 2: Load control input through the D inputs of the ffs J.J. Shann 78
9 Approach : Load control input through the C inputs of the ffs clock gating prevent the clock from reaching the clock input to the ckt if the contents of the reg are to be left unchanged C inputs = Load + Clock * Inserting gates in the clock pulse path produces different propagation delays b/t clock and the inputs of ffs w/ and w/o clock gating. clock skew J.J. Shann 79
10 Approach 2: Load control input through the D inputs of the ffs D i = Load I i + Load i (Load) E.g.: 4bit register w/ parallel load J.J. Shann 7
11 C. Shift Registers ( 76) Shift register: a register capable of shifting its binary information in one or both direction Simplest shift register: unidirectional J.J. Shann 7
12 Shift Register w/ Parallel Load Shift register w/ parallel load: Functional table: D i = Shift Load i + Shift Load Ii + Shift i Clock J.J. Shann 72
13 E.g.: 4bit shift register w/ parallel load D i = Shift Load + Shift Load + Shift i i I i J.J. Shann 73
14 Bidirectional Shift Register Bidirectional shift register direction = shl = shr direction SI of shr SO of shl CLK i + i i D i = direction A i+ + direction A i SO of shr SI of shl J.J. Shann 74
15 Bidirectional Shift Reg w/ Parallel Load Bidirectional shift register w/ parallel load: Mode control Register S S operation No change Shift down Shift up Parallel load J.J. Shann 75
16 D. Ripple Counters ( 76) Counter: a register that goes through a prescribed sequence of states upon the application of input pulses: Input pulses: may be clock pulses or originate from some external source Timing: may occur at regular or irregular intervals of time The sequence of states: may follow the binary number sequence ( Binary counter) or any other sequence of states J.J. Shann 76
17 Categories of counters:. Ripple counters: The flipflop output transition serves as a source for triggering other flipflops. The C input of some or all flipflops are triggered not by the common clock pulses. (not synchronous) 2. Synchronous counters: (E) The C inputs of all flipflops receive the common clock. * T or JK flipflops J.J. Shann 77
18 Binary Ripple Counter Binary countup counter: E.g.: 4bit binary countup ripple counter J.J. Shann 78
19 Observations: FF : C = Clock pulse D = FF : C = ( ) ( ) D = FF 2 : FF 3 : C 2 = ( ) ( ) D 2 = 2 C 3 = 2 ( ) 2 ( ) D 3 = J.J. Shann 79
20 2 3 J.J. Shann 72
21 * Problem of ripple counter: Accumulation of propagation delay E.g.: 2bit binary countup ripple counter CP J.J. Shann 72
22 Binary countdown counter: E.g.: 4bit binary countdown ripple counter Downward Counting Sequence * Modify the figure in p.79: Connect the true output of each ff to the C input of the next ff. J.J. Shann 722
23 Summary: are asynchronous ckts Adv.: simple hardware Disadv.: become ckt w/ delay dependence and unreliable op large ripple counters can be slow ckts the length of time required for the ripple to finish J.J. Shann 723
24 E. Synchronous Counters ( 76) Sync counter: A common clock triggers all flipflops simultaneously. Symbol: Design procedure: We can apply the same procedure of sync seq ckts. Sync counter is simpler than general sync seq ckts. No need to go through a sync seq logic design process. J.J. Shann 724
25 Example E.g.: 4bit sync countup binary counter w/ count enable line Approach : design procedure of sync seq ckt (Ch6) Present state Nest state EN = EN = Output CO D EN = + EN = EN D = ( EN) D2 = 2 ( EN) D3 = 3 ( 2 EN) CO = 3 2 CO: is used to extend the counter to more stages J.J. Shann 725
26 J.J. Shann 726 Approach 2: observation ) ( EN D = ) ( 2 2 EN D = ) ( EN D = 2 3 CO = EN EN D = + = EN
27 Approach 3: an incrementer (Ch5) + D ffs D 3 D 2 D D = EN Incrementer D = EN D = ( EN ) D2 = 2 ( EN) D3 = 3 ( 2 EN) CO = 3 2 J.J. Shann 727
28 Alternative Designs for Binary Counters Two alternative designs for binary counters: Serial counter: serial gating (p.727) Parallel counter: parallel gating lookahead * analogous to the ripple carry adder C C 2 * analogous to the carry lookahead adder ripple C 3 J.J. Shann 728
29 Binary Counter by Using JK FlipFlops E.g.: 4bit countup binary counter w/ JK ffs Binary count sequence: 3bit A 2 A A J.J. Shann 729
30 A 2 A A J = K = EN J = K = EN A J 2 = K 2 = EN A A J 3 = K 3 = EN A 2 A A J.J. Shann 73
31 UpDown Binary Counter Updown binary counter: E.g.: 4bit updown binary counter J.J. Shann 73
32 Upward counting: (p.724) Downward counting: D = EN D ) D = EN = ( EN D ) = ( EN D2 = 2 ( EN) D3 = 3 ( 2 EN) D2 = 2 ( EN) D3 = 3 ( 2 EN) J.J. Shann 732
33 J.J. Shann 733 EN D = ) ) (( EN S S D + = ) ) (( 2 2 EN S S D + = ) ) (( EN S S D + = S = upcounting downcounting EN D = ) ( EN D = ) ( 2 2 EN D = ) ( EN D = EN D = ) ( EN D = ) ( 2 2 EN D = ) ( EN D = Upward counting: Downward counting: Updown counter:
34 Binary Counter w/ Parallel Load E.g.: 4bit countup binary counter w/ parallel load Function table: Load Count I 3 I 2 I I J.J. Shann 734
35 E.g.: 4bit countup binary counter w/ parallel load D = EN D = ( EN) D2 = 2 ( EN) D3 = 3 ( 2 EN) w/o parallel load J.J. Shann 735
36 E.g.: 4bit countup binary counter w/ parallel load D () w/o parallel load J.J. Shann 736
37 Generating Other Count Sequences Generate any count sequence: E.g.: design a BCD counter by using a counter w/ parallel load & async clear J.J. Shann 737
38 J.J. Shann 738
39 F. Other Counters ( 76) Counters: can be designed to generate any desired sequence of states Binary counter (D, E) BCD counter DividebyN counter: modulon counter a counter that goes through a repeated sequence of N states The sequence may follow the binary count or may be any other arbitrary sequence. J.J. Shann 739
40 BCD Counter State diagram & Count sequence: J.J. Shann 74
41 補 充 資 料 : BCD ripple counter (p.737~738) Observations: : 2 : 4 : 8 : C = Count J = K = C 2 = ( ) 8 =, J 2 =, K 2 = (Toggle) 8 =, J 2 =, K 2 = (Reset) J 2 = 8, K 2 = C 4 = 2 ( ) J = K = C 8 = ( ) 4 2 =, J 2 =, K 2 = (Toggle) 4 2 =, J 2 =, K 2 = (Reset) J 2 = 4 2, K 2 = J.J. Shann 74
42 Observations: : 2 : C = Count J = K = C 2 = ( ) 8 =, J 2 =, K 2 = (Toggle) 8 =, J 2 =, K 2 = (Reset) J 2 = 8, K 2 = 8 4 : 8 : C 4 = 2 ( ) J = K = C 8 = ( ) 4 2 =, J 2 =, K 2 = (Toggle) 4 2 =, J 2 =, K 2 = (Reset) J 2 = 4 2, K 2 = 2 4 J.J. Shann 742
43 Synchronous BCD Counter Synchronous BCD counter: E.g.: 4bit sync BCD counter w/ Dtype ff D = D D 2 = = 4 2 D = ( + 4) Y = 8 J.J. Shann 743
44 E.g.: 4bit sync BCD counter w/ Ttype ff T =, T 2 = 8, T 4 = 2, T 8 = , y = 8 J.J. Shann 744
45 Threedecade BCD counter: J.J. Shann 745
46 Counter w/ Unused States n flipflops 2 n binary states Unused states: states that are not used in specifying the sequential ckt may be treated as don tcare conditions or may be assigned specific next states Selfcorrecting counter: Ensure that when a ckt enter one of its unused states, it eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation. Analyze the ckt to determine the next state from an unused state after it is designed. J.J. Shann 746
47 Example: The simplified ff input eqs: D A = A B D B = C D C = B C Two unused states: & J.J. Shann 747
48 The logic diagram & state diagram of the ckt: Analysis Unused states * Selfcorrecting! J.J. Shann 748
49 補 充 資 料 :Ring Counter Ring counter: a circular shift register w/ only one flipflop being set at any particular time, all others are cleared (initial value = ) The single bit is shifted from one flipflop to the next to produce the sequence of timing signals. E.g.: 4bit ring counter T T T 2 T 3 J.J. Shann 749
50 Application of counters: Counters may be used to generate timing signals to control the sequence of operations in a digital system. Approaches for generation of 2 n timing signals:. a shift register (ringcounter) w/ 2 n flipflops 2. an nbit binary counter + an nto2 n line decoder J.J. Shann 75
51 J.J. Shann 75
52 補 充 資 料 :Johnson Counter Ring counter vs. Switchtail ring counter: Ring counter: a kbit ring counter circulates a single bit among the flipflops to provide k distinguishable states. Switchtail ring counter: is a circular shift register w/ the complement output of the last flipflop connected to the input of the first flipflop a kbit switchtail ring counter will go through a sequence of 2k distinguishable states. (initial value = ) J.J. Shann 752
53 E.g.: 4bit switchtail ring counter C E A E AB CE T T 8 T 7 T. T 8 T 3 T 2 T 6 T 5 T 4 J.J. Shann 753
54 Johnson counter: a kbit switchtail ring counter + 2k 2input decoding gates provide outputs for 2k timing signals E.g.: 4bit Johnson counter T 8 T 7 T 6 T 5 T 4 T 3 T 2 T 8 2input decoding gates A B C E 4bit switchtail ring counter The decoding follows a regular pattern: 2 inputs per decoding gate J.J. Shann 754
55 Disadv. of the switchtail ring counter: If it finds itself in an unused state, it will persist to circulate in the invalid states and never find its way to a valid state. Not selfcorrecting! Unused states: 8 J.J. Shann 755
56 Analysis of the ckt: A + = D A = E B + = D B = A C + = D C = B E + = D E = C Binarycoded state table State diagram J.J. Shann 756
57 CE AB CE AB (Unused states) A + = E B + = A CE AB C + = B CE AB E + = C J.J. Shann 757
58 CE AB CE AB * Selfcorrecting! A + = E B + = A CE AB C + = (A + C)B CE AB E + = C J.J. Shann 758
59 Summary: Johnson counters can be constructed for any # of timing sequences: # of flipflops = /2 (the # of timing signals) # of decoding gates = # of timing signals 2input per gate J.J. Shann 759
60 72 Chapter Summary Registers Simplest register ( 7) Register with parallel load ( 7) Shift registers ( 76) Counters Ripple counter ( 76) Synchronous binary counters ( 76) Other counters ( 76) J.J. Shann 76
61 Homework Sections Exercises 7 ~ ~ 22 Homework: 2, 5 Homework: 9, 4, 8, 2, 22 J.J. Shann 76
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