# Cascaded Counters. Page 1 BYU

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1 Cascaded Counters Page 1

2 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls over Requires log 2 N flip flops For example A 4-bit binary counter is a mod-16 counter A counter that counts from 0-9 is a mod-10 counter Page 2

3 A Mod-4 Counter A.K.A. 2-bit counter CLR INC Q1 Q0 N1 N CLR INC CLR CLR INC CLR INC CLR INC CLR INC 01 CLR INC 10 CLR INC CLR INC Page 3

4 A Mod-4 Counter With Rollover Signal CLR INC Q1 Q0 N1 N0 RO Mealy output CLR INC / RO CLR INC 11 CLR 00 CLR INC CLR INC CLR INC 01 The ROLL signal is used to tell other circuitry that the counter is rolling over to all 0 s. CLR INC 10 CLR INC CLR INC Page 4

5 Cascaded Counters Larger counters can be built by combining smaller counters together The rollover signal is used to communicate when the upper counters should roll over Two types of counters Asynchronous Synchronous Page 5

6 Cascaded Asynchronous Counter digit1 digit0 Sequence should be: But we get: roll1 1 2 Mod-4 Counter 1 roll0 2 Mod-4 Counter As a general rule. DO NOT tie the clock inputs on modules to anything but the clock! digit1 0 1 digit roll0 / 1 Page 6

7 Cascaded Asynchronous Counter digit1 digit roll1 Mod-4 Counter 1 roll0 Mod-4 Counter digit1 rements too early digit0 roll0 / 1 digit1 Page 7

8 Cascaded Asynchronous Counter The more stages we add to the counter, the bigger the discrepancy between asynchronous counters and what we expect Stage 1 Stage 2 Stage 3 Expected Async Expected Async Page 8

9 digit1 digit It is possible to modify the circuit to get the correct count sequence, but the roll signal must be glitch free! roll1 Mod4 Counter 1 roll0 Mod4 Counter The transition from the value 1 to 2 (01 2 to 10 2 ) makes it difficult, if not impossible to eliminate glitches. digit1 0 1 digit Possible hazard roll0 / 1 Page 9

10 Ripple Counters When you tie a rollover-like signal to a clock on the next higher digit ripple counter A ripple counter is an asynchronous counter Transitions are not all synchronized to the clock Different flip flops change at different times Similar to gated clocks (seen earlier) Asynchronous circuits are an advanced topic Page 10

11 Another Common Ripple Counter Counts in normal binary: Q3 Q2 Q1 Q T Q Q 1 T Q Q 1 T Q Q 1 T Q Q CLK What s wrong with this design? Page 11

12 Timing Diagram Q0 Q1 Q2 Q0 changes in response to clock edge Only after Q0 changes does Q1 s FF get a clock Only after that does Q2 s FF get a clock Logic depending on Q3 has very little time to react before next clock edge Q3 Net effect is that all the FF s change at different times! Page 12

13 Asynchronous and Ripple Counters Because asynchronous and ripple counters are difficult to use correctly, they are avoided Do not use them in your designs! Violates globally synchronous design priple Always use synchronous counters Page 13

14 Synchronous Counters In a synchronous counter, all flip flops are clocked by the same clock signal They all change at the same time Synchronous counters can be cascaded to create larger counters that are also globally synchronous Page 14

15 A Mod-4 Counter CLR INCQ1 Q0 N1 N0 RO IFL D Q D Q Count Value Terminal Count Roll Over Page 15

16 A Mod-4 Counter CLR INCQ1 Q0 N1 N0 RO IFL D Q D Q Count Value Terminal Count We could make a mod-4 counter from the block shown in red. Roll Over Page 16

17 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Page 17

18 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Count Value Terminal Count Rollover Page 18

19 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Assume that the second timer is already at the terminal count. Page 19

20 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Page 20

21 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Page 21

22 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Page 22

23 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Page 23

24 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV Page 24

25 Cascaded Counters digit0[1:0] digit1[1:0] digit2[1:0] CV CV CV It looks like the signal ripples from counter to counter. How is this different from the ripple counter examples? Page 25

26 Cascaded Synchronous Counter digit roll digit Page 26

27 Cascaded Synchronous Counter Notice that all signals are synchronized with the system clock roll0 roll1 Signals: digit0 digit1 digit2 Page 27

28 A Mod-4 Counter With consolidated rollover logic Count Value IFL D Q Terminal Count D Q A good mod-4 counter ludes the logic within the red block. Roll Over Page 28

29 A Mod-4 Counter dout roll Page 29

30 Cascading two Mod-4 Counters Count Sequence: digit1 digit roll1 roll Increment higher digit s counter when lower digit s counter is rolling over digit1 2 dout roll0 roll digit0 2 dout Page 30

31 Three-digit Mod-4 Counter Can combine any counters that have a rollover signal to make larger counters Combine two 16-bit counters to make a 32-bit counter Combine three mod-4 counters to make a three-digit mod-4 counter digit2 digit1 digit roll1 roll dout roll1 roll dout roll0 roll dout Page 31

32 BCD Counter Combine to create non-binary counters BCD counter digit2 digit1 digit roll1 dout MOD10 roll roll1 dout MOD10 roll roll0 dout MOD10 roll Page 32

33 Hybrid Counters Can combine different kinds of mod counters Combine an 8-bit counter with a 16-bit counter to create a 24-bit counter Combine mod-24 and mod-60 counters to create a digital H:M:S clock Hours Minutes Seconds day dout MOD24 roll hour dout MOD60 roll min dout MOD60 roll sec Page 33

34 D Flip Flop with Asynchronous Clear and Clock Enable Clock Enable (a.k.a. Load) Clear (a.k.a. Reset) Page 34

35 Mod-4 Counter D0 CLK CE CE CEO D1 Page 35

36 Cascaded Synchronous Counter Digit0 Digit1 CEO CLK Reset Digit0 CEO Digit1 Page 36

37 Library Counters Component libraries often have several cascadable counters available Can be cascaded to form desired width Xilinx Library Counters Page 37

38 Summary Mod-N counters are counters that count from 0 to N-1 then roll over Adding rollover logic to counters allows us to cascade counters We can build large counters from smaller ones We can easily build non-binary counters BCD counter HMS clock counter Always use synchronous counters instead of asynchronous counters Page 38

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