DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS"

Transcription

1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is a 4-bit synchronous up/down binary counter. The counter has a count-up clock input (CP U ), a count-down clock input (CP D ), an asynchronous parallel load input (PL), four parallel data inputs (P 0 to P 3 ), an asynchronous master reset input (MR), four counter outputs (O 0 to O 3 ), an active LOW terminal count-up (carry) output (TC U ) and an active LOW terminal count-down (borrow) output (TC D ). The counter outputs change state on the LOW to HIGH transition of either clock input. However, for correct counting, both clock inputs cannot be LOW simultaneously. The outputs TC U and TC D are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH to LOW transition of CP U will cause TC U to go LOW. TC U will stay LOW until CP U goes HIGH again. Likewise, output TC D will go LOW when the circuit is in the zero state and CP D goes LOW. When PL is LOW, the information on P 0 to P 3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop. Fig.2 Pinning diagram. PINNING PL P 0 to P 3 CP U CP D MR TC U TC D O 0 to O 3 Fig.1 Functional diagram. parallel load input (active LOW) parallel data inputs count-up clock pulse input (LOW to HIGH, edge-triggered) count-down clock pulse input (LOW to HIGH, edge-triggered) master reset input (asynchronous) buffered terminal count-up (carry) output (active LOW) buffered terminal count-down (borrow) output (active LOW) buffered counter outputs P(N): 16-lead DIL; plastic (SOT38-1) D(F): 16-lead DIL; ceramic (cerdip) (SOT74) T(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, I DD LIMITS category See Family Specification January

3 Fig.3 Logic diagram (continued on Fig.4). January

4 Fig.4 Logic diagram (continued from Fig.3). January

5 FUNCTION TABLE MR PL CP U CP D MODE H X X X reset (asyn.) L L X X parallel load L H H count-up Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition L H H count-down Logic equations for terminal count: TC U = O 0 O 1 O 2 O 3 CP U TC D = O 0 O 1 O 2 O 3 CP D Fig.5 State diagram. AC CHARACTERISTICS V SS = 0 V; T amb =25 C; input transition times 20 ns V DD V TYPICAL FORMULA FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) January

6 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays CP U O n ns 183 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 74 ns + (0,23 ns/pf) C L ns 52 ns + (0,16 ns/pf) C L ns 143 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 59 ns + (0,23 ns/pf) C L ns 42 ns + (0,16 ns/pf) C L CP D O n ns 183 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 74 ns + (0,23 ns/pf) C L ns 57 ns + (0,16 ns/pf) C L ns 143 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 59 ns + (0,23 ns/pf) C L ns 42 ns + (0,16 ns/pf) C L CP U TC U ns 98 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 39 ns + (0,23 ns/pf) C L ns 27 ns + (0,16 ns/pf) C L ns 68 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 29 ns + (0,23 ns/pf) C L ns 22 ns + (0,16 ns/pf) C L CP D TC D ns 113 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 44 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L ns 73 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 29 ns + (0,23 ns/pf) C L ns 22 ns + (0,16 ns/pf) C L MR O n ns 168 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 69 ns + (0,23 ns/pf) C L ns 52 ns + (0,16 ns/pf) C L MR TC U ns 118 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 49 ns + (0,23 ns/pf) C L ns 37 ns + (0,16 ns/pf) C L MR TC D ns 338 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 119 ns + (0,23 ns/pf) C L ns 92 ns + (0,16 ns/pf) C L PL O n ns 158 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 64 ns + (0,23 ns/pf) C L ns 47 ns + (0,16 ns/pf) C L January

7 V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA ns 118 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 49 ns + (0,23 ns/pf) C L ns 37 ns + (0,16 ns/pf) C L AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Output transition times ns 10 ns + (1,0 ns/pf) C L HIGH to LOW 10 t THL ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L ns 10 ns + (1,0 ns/pf) C L LOW to HIGH 10 t TLH ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L Set-up time ns P n PL 10 t su ns ns Hold time ns P n PL 10 t hold 5 25 ns ns Minimum CP U or CP D ns pulse width; LOW 10 t WCPL ns ns Minimum MR ns pulse width; HIGH 10 t WMRH ns ns Minimum PL ns pulse width; LOW 10 t WPLL ns ns Recovery time ns for MR 10 t RMR ns ns Recovery time ns for PL 10 t RPL ns ns Maximum clock 5 2,5 5 MHz pulse frequency 10 f max 7 14 MHz MHz see also waveforms Fig.6 January

8 Fig.6 Waveforms showing recovery times for PL and MR, minimum pulse widths for CP U,CP D,PL and MR, and set-up and hold times for P to PL. Set-up times and hold times are shown as positive values but may be specified as negative values. January

9 Fig.7 Timing diagram. APPLICATION INFORMATION Some examples of applications for the are: Up/down difference counting Multistage ripple counting Multistage synchronous counting Fig.8 Example of cascaded ICs. January

DATA SHEET. HEF4017B MSI 5-stage Johnson counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4017B MSI 5-stage Johnson counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

DATA SHEET. HEF4508B MSI Dual 4-bit latch. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4508B MSI Dual 4-bit latch. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock 74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo-6

More information

74AC191 Up/Down Counter with Preset and Ripple Clock

74AC191 Up/Down Counter with Preset and Ripple Clock 74AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature

More information

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

8-bit synchronous binary down counter

8-bit synchronous binary down counter Rev. 5 21 April 2016 Product data sheet 1. General description The is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its

More information

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop Rev. 9 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input

More information

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register Rev. 10 21 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an (parallel-to-serial converter) with a synchronous serial data input (DS), a clock

More information

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation

More information

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised March 2002 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS190 is a synchronous UP/DOWN BCD Decade (8421) Counter and the SN54/74LS191 is a synchronous UP/DOWN Modulo-

More information

CD4013BC Dual D-Type Flip-Flop

CD4013BC Dual D-Type Flip-Flop CD4013BC Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors.

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

14-stage ripple-carry binary counter/divider and oscillator

14-stage ripple-carry binary counter/divider and oscillator Rev. 8 25 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a with three oscillator terminals (RS, REXT and CEXT), ten buffered outputs (Q3 to

More information

Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED

More information

74F168*, 74F169 4-bit up/down binary synchronous counter

74F168*, 74F169 4-bit up/down binary synchronous counter INTEGRATED CIRCUITS 74F168*, * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 5 IC15 Data Handbook FEATURES Synchronous counting and loading Up/Down counting

More information

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation

More information

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-

More information

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters DM54161 DM74161 DM74163 Synchronous 4-Bit Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The 161

More information

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The

More information

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger Rev. 5 30 November 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,

More information

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger Rev. 5 29 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn)

More information

SN54/74LS192 SN54/74LS193

SN54/74LS192 SN54/74LS193 PRESEABLE BCD/DECADE UP/DOWN COUNER PRESEABLE 4-BI BINARY UP/DOWN COUNER he SN4/74LS2 is an UP/DOWN BCD Decade (842) Counter and the SN4/74LS3 is an UP/DOWN MODULO-6 Binary Counter. Separate Count Up and

More information

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control 54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control General Description This circuit is a synchronous reversible up down counter The 191 is a 4-bit binary counter Synchronous

More information

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock 54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock General Description This circuit is a synchronous up down 4-bit binary counter Synchronous operation is provided by

More information

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop Rev. 8 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. pplications The is a dual -type flip-flop that features independent set-direct input (S), clear-direct input

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Rev. 6 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features

More information

1-800-831-4242

1-800-831-4242 Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description

More information

1-of-4 decoder/demultiplexer

1-of-4 decoder/demultiplexer Rev. 6 1 April 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications The contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (na0 and na1, an active

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

CD4013BC Dual D-Type Flip-Flop

CD4013BC Dual D-Type Flip-Flop Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit cotructed with N- and P-channel enhancement mode traistors. Each

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate

HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate Rev. 6 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise

More information

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook.

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook. INTEGRATED CIRCUITS Supercedes data of 1990 Oct 23 IC15 Data Handbook 1996 Mar 12 FEATURE Industrial temperature range available ( 40 C to +85 C) DESCRIPTION The is a dual positive edge-triggered D-type

More information

74HC165; 74HCT165. 8-bit parallel-in/serial out shift register

74HC165; 74HCT165. 8-bit parallel-in/serial out shift register Rev. 4 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device

More information

74HC4040; 74HCT4040. 12-stage binary ripple counter

74HC4040; 74HCT4040. 12-stage binary ripple counter Rev. 5 3 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a with a clock input (CP), an overriding asynchronous master reset

More information

Quad 2-input NAND Schmitt trigger

Quad 2-input NAND Schmitt trigger Rev. 9 15 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches

More information

HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP

HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP DUAL-J-K MASTER-SLAVE FLIP-FLOP. SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER HIGH OR LOW MEDIUM SPEED OPERATION - 16MHz (typ. clock toggle rate

More information

74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information

74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information Rev. 4 24 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock (CP)

More information

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE. MEDIUM SPEED OPERATION - 8MHz (typ.) @ CL = 50pF AND DD-SS = 10. MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RES-

More information

HCC/HCF4032B HCC/HCF4038B

HCC/HCF4032B HCC/HCF4038B HCC/HCF4032B HCC/HCF4038B TRIPLE SERIAL ADDERS INERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS FULLY STATIC OPERATION...DC TO 10MHz (typ.) @ DD = 10 BUFFERED INPUTS AND OUTPUTS SINGLE-PHASE

More information

MC14008B. 4-Bit Full Adder

MC14008B. 4-Bit Full Adder 4-Bit Full Adder The MC4008B 4bit full adder is constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. This device consists of four full adders with fast

More information

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance

More information

Description. Table 1. Device summary. Order code Temperature range Package Packaging Marking

Description. Table 1. Device summary. Order code Temperature range Package Packaging Marking 14-stage ripple carry binary counter/divider and oscillator Applications Automotive Industrial Computer Consumer Description Datasheet - production data Features Medium speed operation Common reset Fully

More information

HCC4541B HCF4541B PROGRAMMABLE TIMER

HCC4541B HCF4541B PROGRAMMABLE TIMER HCC4541B HCF4541B PROGRAMMABLE TIMER 16 STAGE BINARI COUNTER LOW SYMMETRICAL OUTPUT RESISTANCE, TYPICALLY 100 OHM AT DD = 15 OSCILLATOR FREQUENCY RANGE : DC TO 100kHz AUTO OR MASTER RESET DISABLES OSCIL-

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook. 1997 Jun 30

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook. 1997 Jun 30 INTEGRATED CIRCUITS IC24 Data Handbook 1997 Jun 30 FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5 V CMOS low power consumption

More information

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter 54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting

More information

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop Dual D-Type Positive Edge-Triggered Flip-Flop General Description The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is traferred

More information

CD4043BC CD4044BC Quad 3-STATE NOR R/S Latches Quad 3-STATE NAND R/S Latches

CD4043BC CD4044BC Quad 3-STATE NOR R/S Latches Quad 3-STATE NAND R/S Latches CD4043BC CD4044BC Quad 3-STATE NOR R/S Latches Quad 3-STATE NAND R/S Latches General Description The CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3- STATE

More information

HCF4028B BCD TO DECIMAL DECODER

HCF4028B BCD TO DECIMAL DECODER BCD TO DECIMAL DECODER BCD TO DECIMAL DECODING OR BINARY TO OCTAL DECODING HIGH DECODED OUTPUT DRIVE CAPABILITY "POSITIVE LOGIC" INPUTS AND OUTPUTS: DECODED OUTPUTS GO HIGH ON SELECTION MEDIUM SPEED OPERATION

More information

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with

More information

74HC74; 74HCT74. 1. General description. 2. Features and benefits. 3. Ordering information

74HC74; 74HCT74. 1. General description. 2. Features and benefits. 3. Ordering information Rev. 5 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual

More information

5495A DM7495 4-Bit Parallel Access Shift Registers

5495A DM7495 4-Bit Parallel Access Shift Registers 5495A DM7495 4-Bit Parallel Access Shift Registers General Description These 4-bit registers feature parallel and serial inputs parallel outputs mode control and two clock inputs The registers have three

More information

HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION

HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION QUIESCENT CURRENT SPECIF. UP TO 20V OPERATION OF LIQUID CRYSTALS WITH CMOS CIRCUITS PROVIDES ULTRA LOW POWER DISPLAY. EQUIVALENT AC OUTPUT DRIVE

More information

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device

More information

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP.

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP. M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. HIGH SPEED fmax = 48 MHz (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.)

More information

HCF4001B QUAD 2-INPUT NOR GATE

HCF4001B QUAD 2-INPUT NOR GATE QUAD 2-INPUT NOR GATE PROPAGATION DELAY TIME: t PD = 50ns (TYP.) at V DD = 10V C L = 50pF BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V

More information

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7-segment decoder driver incorporating input latches and constant current output circuits

More information

8-bit binary counter with output register; 3-state

8-bit binary counter with output register; 3-state Rev. 3 24 February 2016 Product data sheet 1. General description The is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary

More information

MM74HC273 Octal D-Type Flip-Flops with Clear

MM74HC273 Octal D-Type Flip-Flops with Clear MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise

More information

MC14175B/D. Quad Type D Flip-Flop

MC14175B/D. Quad Type D Flip-Flop Quad Type D Flip-Flop The MC475B quad type D flipflop is cotructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Each of the four flipflops is positiveedge triggered

More information

MM74HC174 Hex D-Type Flip-Flops with Clear

MM74HC174 Hex D-Type Flip-Flops with Clear Hex D-Type Flip-Flops with Clear General Description The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity,

More information

MM74HC4538 Dual Retriggerable Monostable Multivibrator

MM74HC4538 Dual Retriggerable Monostable Multivibrator MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicon-gate CMOS technology. They feature

More information

3-to-8 line decoder, demultiplexer with address latches

3-to-8 line decoder, demultiplexer with address latches Rev. 7 29 January 2016 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC

More information

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated

More information

6-BIT UNIVERSAL UP/DOWN COUNTER

6-BIT UNIVERSAL UP/DOWN COUNTER 6-BIT UNIVERSAL UP/DOWN COUNTER FEATURES DESCRIPTION 550MHz count frequency Extended 100E VEE range of 4.2V to 5.5V Look-ahead-carry input and output Fully synchronous up and down counting Asynchronous

More information

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides

More information

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic

More information

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

More information

CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14-Stage Ripple Carry Binary Counters

CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14-Stage Ripple Carry Binary Counters CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14-Stage Ripple Carry Binary Counters Features Wide supply voltage range: 3.0V to 15V High noise immunity: 0.45 V DD (Typ.) Low power TTL compatibility:

More information

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 7 26 January 2015 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin

More information

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1 WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits

More information

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

More information

74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State) INTEGRATED CIRCUITS Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State) 1995 Mar 31 IC15 Data Handbook Philips Semiconductors Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

More information

74AUP1G74. 1. General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger

74AUP1G74. 1. General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 9 6 January 2014 Product data sheet 1. General description The provides a low-power, low-voltage single positive-edge triggered

More information

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs 74HC574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Ordering Code: March 1993 Revised May 2005 The HC574 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated

More information

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 8 25 February 2016 Product data sheet 1. General description The is an 8-bit serial-in/serial or parallel-out shift

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence

More information

CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger

CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger General Description The CD4093B consists of four Schmitt-trigger circuits Each circuit functions as a 2-input NAND gate with Schmitt-trigger action on

More information

HCF4010B HEX BUFFER/CONVERTER (NON INVERTING)

HCF4010B HEX BUFFER/CONVERTER (NON INVERTING) HEX BUFFER/CONVERTER (NON INVERTING) PROPAGATION DELAY TIME: t PD = 50ns (Typ.) at V DD = 10V C L = 50pF HIGH TO LOW LEVEL LOGIC CONVERSION MULTIPLEXER: 1 TO 6 OR 6 TO 1 HIGH "SINK" AND "SOURCE" CURRENT

More information

HCF4070B QUAD EXCLUSIVE OR GATE

HCF4070B QUAD EXCLUSIVE OR GATE QUAD EXCLUSIE OR GATE MEDIUM-SPEED OPERATION t PHL = t PLH = 70ns (Typ.) at CL = 50 pf and DD = 10 QUIESCENT CURRENT SPECIFIED UP TO 20 5, 10 AND 15 PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I I = 100nA

More information

Low-power D-type flip-flop; positive-edge trigger; 3-state

Low-power D-type flip-flop; positive-edge trigger; 3-state Rev. 8 29 November 2012 Product data sheet 1. General description The provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input (D) that meet the set-up

More information

Triple single-pole double-throw analog switch

Triple single-pole double-throw analog switch Rev. 12 25 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a triple single-pole double-throw (SPDT) analog switch, suitable

More information

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012 Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

More information

8-channel analog multiplexer/demultiplexer

8-channel analog multiplexer/demultiplexer Rev. 12 25 March 2016 Product data sheet 1. General description The is an with three address inputs (S1 to S3), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common

More information

74HC238; 74HCT238. 3-to-8 line decoder/demultiplexer

74HC238; 74HCT238. 3-to-8 line decoder/demultiplexer Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive

More information

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse. DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting

More information

Module 3: Floyd, Digital Fundamental

Module 3: Floyd, Digital Fundamental Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

More information

74LVC1G74. 1. General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger

74LVC1G74. 1. General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger Rev. 12 2 pril 2013 Product data sheet 1. General description The is a single positive edge triggered -type flip-flop with individual data () inputs, clock (P) inputs, set (S) and reset (R) inputs, and

More information

.LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M74HC154 4 TO 16 LINE DECODER/DEMULTIPLEXER. HIGH SPEED tpd = 15 ns (TYP.) at VCC =5V

.LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M74HC154 4 TO 16 LINE DECODER/DEMULTIPLEXER. HIGH SPEED tpd = 15 ns (TYP.) at VCC =5V . HIGH SPEED tpd = 15 ns (TYP.) at VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

More information

CD4027BMS. CMOS Dual J-K Master-Slave Flip-Flop. Pinout. Features. Functional Diagram. Applications. Description. December 1992

CD4027BMS. CMOS Dual J-K Master-Slave Flip-Flop. Pinout. Features. Functional Diagram. Applications. Description. December 1992 CD7BMS December 199 CMOS Dual J-K Master-Slave Flip-Flop Features Pinout High Voltage Type (V Rating) Set - Reset Capability CD7BMS TOP VIEW Static Flip-Flop Operation - Retains State Indefinitely with

More information

CD4008BM CD4008BC 4-Bit Full Adder

CD4008BM CD4008BC 4-Bit Full Adder CD4008BM CD4008BC 4-Bit Full Adder General Description The CD4008B types consist of four full-adder stages with fast look-ahead carry provision from stage to stage Circuitry is included to provide a fast

More information