To design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC.


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1 8.1 Objectives To design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. Flipflops are introduced and connected to make a counter. The number of flipflops used and how they are connected determine the number of states and the sequence of the states that the counter goes through in each complete cycle. can be classified into two broad categories: a. Synchronous counters b. Asynchronous counters 8.3 Synchronous In synchronous counter all clocks of flipflops are connected to the same clock signal. Thus, all flipflop outputs change state at precisely the same moment. Table 8.1 shows the states of a 2bit counter. Each state is an increment to its previous state by 1, which means that the counter is an up counter. It is clear from the table that the first flipflop (FF0) toggles at the clock edge (either rising or falling), according to this, this part of the counter is implemented using T flipflop and its input is always at high logic. The second flipflop (FF1) toggles if the output of FF0 is 1. Then this part of the counter is also implemented with T flipflop but with its input connected to the output of the previous flipflop. Table 8.1: 2bit counter. Q1 Q : Digital Logic and Digital Electronics lab. 49
2 Figure 8.1: 2bit synchronous counter. 8.4 Asynchronous In asynchronous counter only the first flipflop (least significant flipflop) FF0 is clocked by a clock signal. The clock of the next flipflops is triggered from the output of the previous flipflop. The inherent delay in the flipflop IC (time since the clock trigger until the signal appears on the output) causes Q1 to be triggered after Q0. Thus the transition of the Q output of the flipflops can never occur at exactly the same time. Asynchronous counters are also implemented using T flipflop. The inputs to all flipflops are connected to logic high and only the clock signal decides if the flipflop shall toggle, according to the output of the previous flipflop. The implementation of a 2bit asynchronous up counter is shown in Figure 8.2. Figure 8.2: 2bit asynchronous counter circuit and timing diagram. Notice that the small delay between the CLK, Q0 and Q1 transitions is not shown in the timing diagram of Figure : Digital Logic and Digital Electronics lab. 50
3 For an asynchronous counter to become an up/down counter the circuit in Figure 8.3 is connected to the clock of each flipflop (except FF0 of course because it is connected to CLK). Figure 8.3: Up/Down logic for asynchronous counters. 8.5 Counter Circuits Design Procedure The design procedure of counter circuits depends on the counter type. For asynchronous counter it is straight forward and it is explained through the following example. Example 8.1 Design a logic circuit that counts from 0 to 15 using asynchronous counter. Table 8.2: 4 bit counter. Q3 Q2 Q1 Q : Digital Logic and Digital Electronics lab. 51
4 Solution: To count from 0 to 15 there is 16 states which mean 4 flipflops are needed. By default when designing asynchronous counters, all flipflop inputs are connected to 1 and only the first flipflop is trigger with a clock input. By inspecting Table 8.2, Q1 is toggled when Q0 changes from1 to 0. Q2 is toggled when Q1 changes from 1 to 0. Q3 is toggled when Q2 changes from 1 to 0. The counter logic circuit is shown in Figure 8.4. Figure 8.4: Asynchronous 4bit counter of Example 8.1 For synchronous counter, the design procedure is the same procedure of designing using flipflops, starting from the state diagram and ending with the logic circuit. Example 8.2 Design a logic circuit that counts from 0 to 4 then back to 0 only if an input signal is 1. Use synchronous counter. Solution: Step one: Figure 8.5 shows the state diagram. Figure 8.5: Example 8.2 state diagram : Digital Logic and Digital Electronics lab. 52
5 Step two and three: The state and excitation tables are shown in table 8.3. Table 8.3: State and excitation tables of Example 8.2. Current state Input Next state Flip flop 1 Flip flop 0 Q1 Q0 U Q1 + Q0 + J1 K1 J0 K X 0 X X 1 X X X X X X 0 0 X X 0 1 X X 0 X X 1 X 1 Step four: Construct Kmaps for each flipflop inputs (J and K) J0=U Figure 8.6: Kmap for J0 in Example : Digital Logic and Digital Electronics lab. 53
6 Figure 8.7: Kmap for K0 in Example 8.2. K0= U Notice that even though the implementation is with JK flipflop the result is that K0=J0 then it is a T flipflop. J1=K1=Q0.U Figure 8.8: Kmap for J1=K1 in Example 8.2. Step five: The logic circuit is implemented in Figure : Digital Logic and Digital Electronics lab. 54
7 Figure 8.9: The logic circuit for Example : Digital Logic and Digital Electronics lab. 55
8 PreLab 8 1 Design a synchronous counter that counts from 0 to 7 if an input R is high and from 7 to 0 if the input R is low. You are required to draw the state diagram, the state table, the excitation table. Then to obtain the inputs to the flipflops (J1, K1, J2, and so on). But you are NOT required to draw the counter logic circuit. Lab Work 8 Use the synchronous 4bit counter IC 74ls193 and 3*8 decoder IC 74ls138 to implement a counter that counts from 2 to 5. Homework 8 1. Design a 2 bit asynchronous up counter using the JK flip flop shown in Figure 8.10 (take care that the flip flop has a rising edge clock). Figure 8.10: Positive edge JKflip flop 2. Using the bit counter you used during your lab work, design an up counter that counts from 2 to 12. To detect the presence of 12, you may use active low 3*8 decoder : Digital Logic and Digital Electronics lab. 56
9 Figure 8.11: up down counter. 3. Using the bit counter you used during your lab work, design an up/down counter that will count up if an input X is 1 and will count down if X is 0. You can use ON LY one clock for both the COUNT UP and the COUNT DOWN terminals : Digital Logic and Digital Electronics lab. 57
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